From the Editor

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Marketing people have been trying for years to figure out the best ways to reach professional engineers.  We are, apparently, an elusive prey. Recently, there has been much wringing of hands with the realization that engineers don't act like "normal" people when it comes to virtual communication channels like facebook, twitter, virtual conferences, and online chat. Are the people who create technology techno-phobic? Do we slave away all day over hot oscilloscopes just to go home at night to a life of log cabins, wood fires, and vegetable gardens? This week, we look at the role virtual communications play in the life of a fictitious but not-that-unrealistic engineer.

We've extended the deadline for the final Journal Forum Posting competitionPost something creative and you could walk away with the final $500 amazon.com gift certificate! 

Thanks as always for reading. We encourage you to share your thoughts in the new easier-to-use comments area right below the articles; don't be shy. Or you can get a lively discussion going on our new FORUMS.

Kevin Morris - Editor, FPGA Journal


Industry News

September 01, 2010

Tiny Low Frequency Clock Chip Supports Long Duration Timing from 1ms to 9.5hrs

C-to-FPGA Integration Accelerates Prototyping 10X

August 31, 2010

Technical Education on Digital Signal Processing, FPGAs and Embedded Processors

HDL Works Presents 'IO Checker 2.0'

August 30, 2010

SoCIP Road Shows to Stop at Shenzhen, Chengdu and Xi’an

GateRocket Teams With AcconSys To Distribute Industry-Leading FPGA Verification and Debug Solutions In China

S2C Announces Virtex-6 Based 4th Generation Rapid SoC Prototyping Solution

2A, 42V Boost Converter Now Offered in High Temperature "H" & "MP" Grades

August 26, 2010

Mentor Graphics Collaborates with GLOBALFOUNDRIES to Provide Easier Debugging Capability to IC Designers

August 25, 2010

Synopsys DesignWare SATA IP Enables First-Pass Silicon Success for Global Unichip Corporation

Microsoft Research uses Lyrtech SFF SDR development platform for experimental ‘white space’ device

7-Channel I2C-Controlled PMIC for High Power 1-Cell Li-Ion Systems

August 24, 2010

Mercury Computer Systems Launches Intel Core i7-Based OpenVPX Solutions for ISR Applications

Synopsys Announces Immediate Availability of DesignWare MIPI M-PHY IP in 40-nm Process Technology

Rail-to-Rail SiGe Op Amps Offer Unmatched Speed-Power Efficiency

August 23, 2010

Synopsys to Host First Synposium Virtual Event

August 19, 2010

Unison Ultra Tiny Linux OS Now Available for Actel SmartFusion Devices

Breakthrough 20V Nanopower Switching Regulator Provides 50mA Output with Only 720nA of Quiescent Current

August 18, 2010

InPA Systems Inc. Targets Active Debug™ for Rapid Prototyping

Feature Articles

Socially Inept

Do Engineers Fail at Virtual Connections?

by Kevin Morris

It's 4:45AM. Charles hits "snooze" one last time on his alarm clock. He can wait another 8 minutes before trying to really wake up for his 5AM conference call with Europe. His status report is 80% finished on his laptop, which waits in "hibernate" by his bed. His smartphone is on his nightstand, next to his bluetooth headset. He tells himself he's pretty much ready for the meeting.

4:53AM - the alarm beeps again and Charles forces his eyelids apart, rolls out of bed and stumbles down the hallway to the kitchen. The espresso machine is already warmed up. He drops in a coffee pod, places a cup below the spout, and presses the "Lungo" button. He wants the extra kick to keep him awake through his call. The 60-second espresso pull feels like an eternity and he bats his eyes into focus as the dark brown liquid slowly lightens. Finally, the machine clicks to a stop and he trundles back down the hall toward his bed, cuddling the warm mug with both hands.  Read More

Debug Doppelgänger

InPA Aims to Simplify FPGA-based Prototypes

by Kevin Morris

There is an I After All

But Seriously, Folks, It was a Team Effort

by Kevin Morris

Drag-and-Drop vs. HDL?

by Dick Selwood


Adept Alternative

Aldec Turns up the Simulation Heat

by Kevin Morris

Xilinx Pwns Space

Is New Rad-Hard FPGA Family a Game-Changer?

by Kevin Morris

Persistent Precision

Mentor Synthesis Makes Steady, Stealthy Progress

by Kevin Morris

Lattice Turns up the Tools

Diamond Re-vamps Design Experience

by Kevin Morris


Observations: 1. Charles needs

Observations:
1. Charles needs some trust-worthy spam control.
2. I'm Charles in so many ways.
3. Ditto Remy, except maybe "Charles gets around to reading his FPGA Journal four days after it arrives electronically."

Fun post.
Posted on 09/03/10 at 6:46 AM
by: jcappello

Nice story, but you forgot the F

Nice story, but you forgot the FPGA journal in the email inbox smiling
Posted on 09/02/10 at 4:16 AM
by: Remy

Are Engineers Socially Inept or Just Busy?

We looked at a day in the life of a typical engineer (click here). Does this sound like one of your days? Do you have time for social media? Are engineers different f...
Posted on 08/31/10 at 12:47 PM
by: kevin

FPGA-based Prototyping

We took a look at the difficulties involved in FPGA-based prototyping (click here) and talked about a startup that aims to improve the situation. What do you think?
Posted on 08/25/10 at 11:58 AM
by: kevin

Functional coverage & random gen - when do we converge?

In response to war_isbest:

You raised 2 important discussions here - one on ABV and the other on CDV. Let me provide my views on CDV here.

As you have noted, you ran 30-50K random vectors, still not sure..that's always the case unless you have an ...
Posted on 08/19/10 at 5:36 PM
by: cvcblr

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On Demand

Virtex-6HXT Lab Demo (VIDEO)

This video shows a quick lab demo of the Virtex-6HXT, the industry's highest bandwidth FPGA, featuring 24GTH transceivers (11+Gb/s) AND GTX transceivers (6.6Gb/s) for a total of 72 Transceivers. This FPGA combines the world's highest performance FPGA fabric with the world's highest performance serial transceivers, sampling now! Please subscribe and stay tuned for future demos of our superior performance and exclusive compliance to a variety of optical specs.

Simpler, Smarter Platform for Differentiated Digital TVs (VIDEO)

The Spartan-6 FPGA Consumer Video kit provides a simpler way to update and modify video algorithms, and incorporate new video standards such as DisplayPort and V-by-One-HS. The advanced integrated design environment allows designers to efficiently develop and test high speed serial interfaces like LVDS and TMDS and debug HDMI or DVI-based solutions. The Spartan-6 FPGA Consumer Video Kit offers everything designers need to implement features for today and tomorrow's market. Watch this short video to learn more.

Mixed-Signal Power Management: Bridging the Analog-Digital Divide with Mixed-Signal FPGA Graphical Design Configuration Methodology (WHITE PAPER)

The management of power at the system level is a challenge faced by all system designers, but designers face a daunting divide between digital and analog when considering tools, practices, and methodologies. A new methodology developed by Actel, implemented in a new design tool, addresses the challenges, and eliminates barriers to delivering user-configurable mixed-signal power management without the need to reprogram circuit design changes to implement configuration changes.

Actel FPGAs for Handheld Portable Solutions (CHALK TALK)

With the industry's lowest power and widest range of small packages, it's no wonder Actel IGLOO® FPGAs can be found in the latest handheld portable devices. Actel has been designed into a wide array of handheld devices, including smartphones, eBooks, cameras, medical devices, industrial scanners, military radios, and the list goes on. Actel IGLOO low power FPGAs bring reprogrammability, design security, integration, small form factor, and live-at-power-up operation to handheld portable applications. In this webcast host Amelia Dalton chats with Naseem Aslam about Actel solutions for handheld portable applications.

Using SATA for SOC Solutions on 40-nm Transceiver FPGAs (VIDEO)

With applications needing to store more data for longer periods of time, SATA provides an efficient, cost-effective storage interface. Watch this 7-minute video for a demo showing how easy it is to take advantage of the data storage capabilities of SATA using 40-nm transceiver FPGAs.

Next Generation System Design – Platforms versus Tool-Chains (WHITE PAPER)

This paper will enumerate the benefits of a platform-based system design approach. The original electronic design process built by linking tools together has remained largely unchanged for decades (i.e. tool-chains). A layered platform architecture unifies PCB, FPGA and embedded software development into one application. At the foundation is a unified data model that enables numerous data management benefits including versioning and ECO management. Companies switching to a platform based design process are doubling their productivity as compared to traditional tool-chains.

Guaranteeing Silicon Performance with FPGA Timing Models (WHITE PAPER)

Altera® timing models provide a simple and easy way to verify the timing of FPGA designs without the need to perform full physical electrical extractions and simulations. The three different operating corners available for 65-nm and newer FPGAs provide a thorough coverage of the time delays within the recommended operating conditions.

Power-Efficient Virtex-6 AMC With Versatile FMC IO Site (CHALK TALK)

Join Amelia as she chats with experts from Linear Technology, Xilinx, and Lyrtech about getting ATCA up and running with a super-slick development kit - complete with power by Linear Technology, Virtex-6 FPGAs by Xilinx, and an innovative board set from Lyrtech. Also, remember to click the paperclip on the viewer so you can receive a 10% discount on the Perseus 601X board from Lyrtech andor a chance to win one of two iPod Shuffles courtesy of Xilinx

Single-Event Effect Mitigation in RTAX-DSP Space-Flight FPGAs (WHITE PAPER)

When high-energy ions present in space strike the substrate of an IC, their impact can cause momentary current/voltage pulses in the IC’s circuitry. When these pulses are sufficient to change the data on the circuit, they are referred to collectively as single-event effects (SEEs).