Power Management in an Embedded Multiprocessor Cluster (WHITE PAPER)
Coherent microprocessor clusters, having localized instruction and data caches per CPU, require special techniques to maintain consistency between localized cache contents and their common address region. For embedded systems, designers typically apply snoop-based schemes to maintain memory coherence. This scheme introduces ownership attributes of local cache lines, which are posted throughout the cluster upon intent to use or change.
As a core acquires ownership of a particular cache line with intent to modify - e.g. due to a pending store operation, peer CPUs are notified and will update their cache line on demand. Similarly, localized access to cache lines due to pending load instructions can stay localized if permitted by ownership attributes. Competing access to a particular cache line must be ordered to maintain consistency. The implemented snoop protocol supports “MESI” style cache line attributes to mark lines as modified, exclusive, shared or invalid. Duplication of L1 tags per CPU promotes parallel operation of execution pipeline and snoop request processing.
Author: Matthias Knoth, MIPS Technologies
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