The MEMS Testing Quagmire
Players are Increasingly Looking for Extrication
Testing is an unfortunate but important requirement for being in the chip business. Unfortunate because it’s expensive and, well, annoying. Important because no one would trust electronics that had never been tested. And systems builders would end up throwing a lot of useless stuff away. It’s the “failure costs 10x as much for each later stage at which it’s caught” thing. Read More
latest news
February 22, 2012
February 21, 2012
Saelig's New Range of PCIe Digital I/O Cards
February 17, 2012
Agilent Technologies’ Latest Genesys Software Enhances RF System Design
Agilent Technologies Introduces Industry’s Most Comprehensive LPDDR3 Compliance Test Application
February 16, 2012
Agilent Technologies Adds Frequency Spectrum to Arbitrary Waveform Generator, Enhances Versatility
February 15, 2012
Saelig Debuts Unique Circuit Track Current Probe
February 14, 2012
Tektronix Donates Electronics Test Equipment to Washington State University Vancouver
February 13, 2012
Saelig's New Fault Tracker Detects Problems in Complicated Electrical Control Systems
February 10, 2012
February 06, 2012
February 01, 2012
Symtavision to showcase new versions of SymTA/S and TraceAnalyzer at Embedded World 2012
Two Conversations at Once
octoScope Reduces the Cost of MIMO Testing
Necessary and Sufficient?
A Closer Look at Cell-Aware Modeling
Are You Covered?
Software Test Coverage Isn’t as Straightforward as You Might Hope
Editors' Blog
What Comes Around… Is Reflected?
posted by Bryon Moyer
A couple years ago at DesignCon, Intel proposed a new way of testing the insertion loss of differential traces on a PC board. A couple years later, it’s being incorporated into test equipment. (6-Feb)
Validating Serial Protocols
posted by Bryon Moyer
If you want to convince yourself that your super-fast protocol running on a high-speed serial link really works in the real world, you need to test it with something that can actually run at speed. (14-Dec)
Closing the Thermal Loop
posted by Bryon Moyer
Mentor does something with thermal that electrical folks had to do a while ago. (12-Dec)
Describing User-Defined Faults
posted by Bryon Moyer
The Cell-Aware fault modeling approach allows ad hoc faults to be identified, but how do you communicate those faults to the test-generation tools? Especially if you have some faults you want to define by hand? (28-Nov)
Fighting Fire with Fire?
posted by Bryon Moyer
If you want to identify things on a wafer that might get in the way of high-fidelity EUV exposure, what would you use? (8-Nov)
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