The Power of Tcl in PlanAhead
In this episode of Chalk TalkHD Amelia chats with Tori Darien from Xilinx about using Tcl in Xilinx’s PlanAhead tool for FPGA design. Amelia throws her some examples, and Tori walks us through how to work them using PlanAhead’s Tcl interface.
Chalk Talk sponsored by Xilinx
“Smart” Connected Home Entertainment with Android
Experience the SmartCE (Connected Entertainment) for Android platform from MIPS Technologies in this new video demonstration. The SmartCE Platform enables MIPS licensees and their customers to bring differentiated connected entertainment solutions to market quickly.
Troubleshooting and Fast Fault Isolation with VTOS
Troubleshooting and quickly isolating faults is of tremendous value for reducing the time to redesign or repair failing boards. This process can cost a company millions of dollars each year. Supporting OMAP, Sitara, QorIQ, PowerQUICC and PowerPC, this paper describes how using an interpreter that allows the execution of a full test suite for verifying a design or an individual test for fault isolation can dramatically improve quality and reliability with Kozio’s Verification and Test OS (VTOS™). It describes how memory errors can be isolated to ECC (Error Control Coding), single-bit, row, column, and correlated to a part’s reference designator.
Sponsored by: Kozio
Memory Testing 101 – Avoid the Train Wreck
Memory is fundamental to the “sanity” of an embedded system. Inadequate memory testing is posing critical challenges to designers and indirectly manifesting considerable consequences at some of the biggest names in the electronics business. Today’s embedded systems consist of multiple memory types including SDRAM, LPDDR2, DDR3, FLASH, EEPROM and more, along with multiple protocols including GPIO, PCI, SPI and I2C. This paper will review a comprehensive and flexible Verification and Test Operating System (VTOS™) solution that includes a suite of memory tests that verifies the design for correctness and production readiness.
White Paper sponsored by Kozio
Developing Software for Embedded Systems on FPGAs
FPGAs are becoming more common in embedded design. See how easy it is to develop embedded system software for FPGAs using the popular Nios® II soft processor. In this 5-minute video you'll learn about the software development flow for the Nios II processor and see the Nios II Embedded Evaluation Kit, Cyclone® II Edition, in action. You'll also see a graphic demo showing the high performance of the Nios II processor with hardware accelerators.
Design Made Easy With the SmartFusion Customizable System-on-Chip and State of the Art Software Tools
Since the early years of embedded processor design and FPGA design, silicon advancement and design techniques for each have evolved independently. In the real world there are many FPGA designs without embedded processors and many embedded systems that neither have nor need an FPGA. This leads to two very distinct design flows, styles, and engineering disciplines. The relatively recent addition of SmartFusion® customizable system-on-chip (cSoC) devices adds the complexity of analog into the mix.
White Paper sponsored by Microsemi
A Platform for Reducing Verification Time and Improving Reliability of Embedded System Hardware
In this whitepaper the author reviews how leveraging VTOS during the prototype phase can assist engineers in overcoming the challenges design complexity exerts on product development, manufacturing, and overall time-to-market. Readers will gain insight into how they can replace today’s ad-hoc board level verification approaches with an ordered methodology that enables designers to automatically validate their own hardware designs, optimize system performance, and simplify the process of integrating new hardware with new software.
White Paper sponsored by Kozio
Embedded Design Verification Best Practices Short Video
Watch this short video on Embedded Design Verification Best Practices and learn how to verify embedded designs for correctness and reliability utilizing a NEW approach employing a Verification and Test OS (VTOS™).
Preparing for Google TV
Google and partners recently announced Google TV—an open, architecture-neutral platform that will bring the full web experience to television viewing. Given the fact that MIPS licensees lead in the digital home today, it is likely that there will be a large number of future Google TV systems based on the MIPS architecture. Leveraging our work with Android and our ongoing relationship with Google, MIPS is in an excellent position to work with our licensees as Google TV moves beyond initial reference platforms and into mainstream development within the digital home market. By designing your SoC to the right specifications now, you can be ahead of the market when the Google TV code is available in open source in 2011. In this paper, we will provide you with an in-depth description of hardware requirements and recommendations for developing an SoC that will support the Google TV operating system!
White Paper sponsored by MIPS
Intel Atom™ Processor with built-in Altera Arria® FPGA
In this Chalk TalkHD Amelia talks to David Schmidt of Arrow about the new Intel Atom™ processor with an Altera Arria FPGA built right into the package.
Chalk Talk sponsored by Arrow
High-Reliability in FPGA Design - SEU Mitigation
Neutrons are coming for you and you'd better be prepared. Whether we like it or not, SEUs (Single Event Upsets) are becoming a bigger and bigger problem for our designs, especially for high realibility systems. If you thought SEUs couldn't mess up your next design because you aren't designing something destined for space, you need to think again. In this episode of Chalk TalkHD, I chat with Jeff Garrison of Synopsys about the how we can battle SEUs (on the ground or in the air) with the latest generation of design tools.
Chalk Talk sponsored by Synopsys
Timing Closure in FPGA Designs Made Easy with PlanAhead
In this episode of Chalk TalkHD Amelia chats with Frederic Rivoallon of Xilinx and they attempt to unravel the mysteries of timing closure and reveal that yes, you can get timing closure right the first time in your next design.
Chalk Talk sponsored by Xilinx
PowerPC to MIPS® Architecture Migration Guide (REVISED)
Software investment is the biggest ticket item in any project. Hence it is important to choose an instruction set architecture (ISA) that offers a truly scalable solution for future development. To address various embedded market segments, MIPS Technologies offers distinct, binary-compatible families of processor cores that span applications from 32-bit microcontrollers all the way to 64-bit multi-threaded, superscalar many-core processors for networking infrastructure, and numerous digital consumer markets in between. Since one can seamlessly scale the performance range between a wide array of processors, the MIPS® architecture offers an ideal path for protecting software investment on a new design or a follow-on/upgrade to an existing project. This paper illustrates the ease of migration from the Power to MIPS architecture, and highlights the areas that users need to focus on during this process.
White Paper sponsored by MIPS
Is Your Memory Design Correct and Reliable?
Learn how quickly and easily you can run a comprehensive memory test and uncover design and reliability issues. In this video, a memory failure is detected only in "burst" mode, while passing all other tests. A second development board passes all the tests.
Optimizing Performance, Power, and Area in SoC Designs Using MIPS® Multi-threaded Processors
Hardware-based multi-threading technology has for some time been known in the industry as a feasible technique for improving system performance, but not too many people are aware of just how much traction the technology has gained since its early implementations in the 1960s. This article provides a brief history of hardware based multi-threading and some examples of its commercial adoption so far. It then gives an overview of the fundamental value of multi-threading in hardware, and describes MIPS Technologies’ multi-threading architecture and product offerings. The article also provides several multi-threaded application examples—including those in the areas of driver assistance systems and home gateways—to demonstrate the broad applicability of multi-threading in real-world applications.
White Paper sponsored by MIPS