High-Reliability in FPGA Design - SEU Mitigation
Neutrons are coming for you and you'd better be prepared. Whether we like it or not, SEUs (Single Event Upsets) are becoming a bigger and bigger problem for our designs, especially for high realibility systems. If you thought SEUs couldn't mess up your next design because you aren't designing something destined for space, you need to think again. In this episode of Chalk TalkHD, I chat with Jeff Garrison of Synopsys about the how we can battle SEUs (on the ground or in the air) with the latest generation of design tools.
Chalk Talk sponsored by Synopsys
Everything You Wanted to Know About SOC Memory*
More on-chip silicon is devoted to memory than to anything else on a SOC and yet memory is often added as an afterthought. This White Paper discusses the many alternatives for on-chip and off-chip memory usage. It discusses the essentials of SOC memory organizations, on-chip SRAM and DRAM, local memories and caches, on-chip non-volatile memories, and memory controllers for off-chip memory. It covers the difference between 6T and 4T SRAM designs, the system design ramifications of NAND and NOR Flash ROM, and how DDR2 and DDR3 SDRAMS compare.
White Paper sponsored by Tensilica
FPGA Design Methods for Fast Turnaround
This paper takes an in depth look at a variety of techniques to help you speed up your synthesis iterations. Whether the goal is aggressive performance or to get a working initial design or prototype on the board as quickly as possible, this paper provides information on traditional and new techniques that accelerate design and debug iterations.
White Paper sponsored by Synopsys
Hierarchical Design Flows: Design Preservation & Team Design
In this episode of Chalk TalkHD, Amelia chats with David Dye of Xilinx about how Hierarchical Design methodologies and Team Design can accelerate your next FPGA design and get those team members of yours working productively together. With these tools and techniques, two million logic elements won't seem like that much after all.
Chalk Talk sponsored by Xilinx
Teradici Success Story
Synopsys and Teradici: ASIC Prototyping Made Fast and Efficient with Synplify Premier
White Paper sponsored by Synopsys
IP and Process Solutions for Energy-efficient PMICs
In this episode of Chalk TalkHD Amelia chats with Ravi Mahatme from ARM and King Ou from GLOBALFOUNDRIES about how IP and process solutions can help solve our power management problems.
Chalk Talk sponsored by ARM
SmartFusion Customizable System-on-Chip: Intelligent, Innovative Integration
The whole point of an FPGA is flexibility. We could also mention integration and say instead that the whole point of an FPGA is flexibility and integration. But then there is cost savings. So the whole point of an FPGA is flexibility, integration and cost savings. Yet there is also power reduction. And then there’s security.
White Paper sponsored by Microsemi
Catapult C Synthesis Designing a JPEG Compression Engine
Amelia Dalton finds out that designing hardware with high-level languages can be both easy and fun as she and Stuart Clubb of Mentor Graphics walk you through the design of a hardware JPEG encoder using C++.
Chalk Talk sponsored by Mentor Graphics