Elliptic Technologies Delivers Hardware Root of Trust
Sometimes even the circuit designer doesn’t know how the chip works. And that can be a good thing.
If you’re designing a chip or a system that includes security features, anti-tampering mechanisms, DRM protection, or defenses against DPA attacks, it’s probably better if you don’t know how it all works. That kind of stuff is mysterious. Secret. Black magic. And there are practitioners of these dark arts who are far more skilled than mortals like you or me. For they dwell in the deep places, apart from the rest, shunning the daylight and the company of men. And we call them Elliptic Technologies.
Construction at the End of the Road
Those who build roads are fundamentally different from those who use roads.
Those who build roads immerse themselves in every detail of the route. They know the distances, the hills and valleys, the rivers and forests, the grades and angles, the weather, and the wildlife. They have considered every aspect of the particular journey and imagined and re-imagined the trips of the travelers to come. They have contemplated every contingency, every possibility, in an attempt to craft a safe, smooth and seamless experience.
Those who use the roads are insulated from those myriad details. They ride along with the cruise control set at speed limit plus four, GPS ticking off the miles until the exit, wondering quietly whether their podcast episode will finish before or after this stretch of highway terminates. If the road engineers did their jobs well, the driver’s day will be completely unremarkable, the requirements on their skills and awareness minimal, their safety and security all but assured.
Cell-Aware: Meet Slack-Based. And STAR: Meet eFlash.
Ah, the air has cooled. The sun lolls about at a low angle for a few tentative hours. Morning frosts seal the fate of any remaining tender plants. Here in northern Oregon, the Gorge winds blow random gale-force patterns, making it unnecessary to sweep the leaves off of the patio. And, slightly farther north, it’s ITC (that would be the International Test Conference) season, in Seattle this year.
Which means it’s the season for test announcements by EDA companies. Synopsys made some noise, but not with one big blockbuster new thing; rather they assembled a couple of newsy bits that, summed together, merit some discussion.
Just to organize my thinking here, so that I don’t get us lost, there are two basic announcements: Cell-aware+Slack-based testing and STAR for eFLASH. The first involves two subtopics that we should review first.
New RISC Processor for SoC Developers is Yours for the Taking
“There are two major products that came from Berkeley: LSD and Unix. We don't believe this to be a coincidence.” – Jeremy S. Anderson.
Ready for some radical, left-field (not to say left-wing) thinking? Believe in free love, sharing, and open markets? Step right this way. We’ve got something for you.
Oh, goody. It’s another new microprocessor instruction set.
The great minds at the University of California at Berkeley (that’s “Cal” to insiders) have added a lot to our community over the years. Berkeley was the source of some early RISC processor research and the birthplace of Sun’s famous SPARC processor. And its Big Kahuna, Dr. David A. Patterson, PhD., is professor (and former chair) of Computer Science at Berkeley, as well as being an IEEE and ACM Fellow and recipient of the John von Neumann Medal. You may know him as the Patterson in Hennessy & Patterson, authors of the authoritative computer design bible. A real computer nerd, in other words.
A Whole New Way of Switching
I love surprises like this. You go into what promises to be a wonky, even dull, conference presentation – and come out agog.
That’s exactly what happened to me at the recent ICCAD in San Jose. It was a presentation based on a collaboration between the University of Michigan, Shanghai Jiao Tong University, and National Tsing Hua University about some placement or routing algorithm, but it happened to involve a transistor type that I’d never heard of. And… I don’t know, there was something about the regularity of it, perhaps its elegance, illuminated through a very lucid presentation, that caught my fancy. Heck, even with no prior knowledge, I could actually follow most of the talk. That was exciting enough. Great success!
So… what was this thing? It was a way of implementing logic on a fabric of single-electron transistors (SETs). In fact, a reconfigurable fabric. This could be your new FPGA some years hence. But, while I could follow the logic of the presentation, I had no idea what a SET was, nor did I understand why certain constraints existed that affected the algorithms presented.
Calypto’s Catapult 8 Takes Us Higher
Bob killed the headlights and put the car in park. We sat in silence. Eerie lights danced on the horizon. First east, then west, and then straight up into the night sky. We watched with mouths agape as the lights came closer (and closer), only to quietly fade away. A UFO in our midst? Not quite. HLS. Most of us have been watching the skies in hopes for the arrival of High Level Synthesis for years. Steering today's HLS-powered flying saucer is my guest Mark Milligan (Calypto Design Systems). Mark is here to reveal the mysteries of Catapult 8. He'll shine a light on how HLS is powering image processing and video applications, and explain how we can get to design closure from the top or the bottom. Also this week, we introduce a kickstarter campaign that aims to bring fashion-forward wearable fitness monitors to your next holiday wish list.
Can an Asymmetrical Metronome Turn Process Delay Into Product Advantage?
With the production arrival of Broadwell, Intel has finally executed the ‘tick’ onto their impressive 14nm FinFET process. Broadwell is built on the Haswell microarchitecture, introduced some half-dozen quarters back on the 22nm FinFET process. The question under discussion is when and where Intel will execute the ‘tock’ onto the new Skylake microarchitecture.
The possible answers to that question are so fascinating because of the six-quarter (being kind) delay bringing up the 14nm FinFET process and the Broadwell products. Given that [a] Broadwell is a modest architectural step from Haswell and [b] Skylake is engineered to take full advantage of the 14nm FinFET process, a reasonable conjecture is that Intel will have an asymmetrical tick-tock metronome on 14nm. In plain English: there is little reason that Skylake should experience a six-quarter delay; the new microarchitecture ought to be “waiting in the wings” and ready be designed into mobile, laptop, desktop and server products … by no means in that order.
Soft Machines Uses Combination of Tricks to Improve Performance
Still trying to juggle those flaming chainsaws? Splendid, because now we’re going to see how it’s done.
Last week we introduced Soft Machines and its VISC processor, a new CPU design that runs native ARM code even though it’s not an ARM processor. Soft Machines says VISC can also be tailored to run x86 code, Java code, or just about anything else the company decides is worthwhile. It’s a tabula rasa microprocessor: able to run just about anything you throw at it.
Its other major trick is that it can extract more single-thread performance out of a given binary program than any other CPU. And do so without expending a horrendous number of transistors or consuming planetary levels of energy. Let’s start with that part.
Soft Machines’ VISC Processor Takes an Unorthodox Approach
Excuse me while I juggle these flaming chainsaws. While riding a unicycle on a tightrope crossing over Niagara Falls. Blindfolded. Challenging enough for ya?
That’s essentially what a new company called Soft Machines is attempting. It’s a new firm with an entirely new microprocessor design that is taking on the two toughest challenges in the business: how to increase performance while reducing power, and how to run programs written for other processors. Oh, and they’re competing with ARM for embedded RISC processor cores. And then they’ll be taking on Intel and AMD with x86 processors. Challenging enough for ya?
It’s not every day you get to see a brand new microprocessor company. What do you think this is – 1998? Yet Soft Machines thinks it’s cracked the secret code to making embedded processors that are both fast and small, quick yet power-efficient, new yet totally compatible with existing binary code.
Are You Ready for Tomorrow?
There are times when you shouldn't really think too deeply about things. Last week I was driving along the motorway from London to Winchester. While accelerating to overtake, I saw the engine pass through 4,000 rpm, and I wondered about each piston moving from stationary at top dead centre to stationary at bottom dead centre and then back to top dead centre 50 times a second. (Geeky? Moi?) Sadly, I can't perform in my head the sum that would calculate the speed at which each piston was moving at its fastest, but it must be pretty speedy, and that cycle of movement would be putting all sorts of stresses on all sorts of metal parts. I eased my mental stress by consoling myself that, at least in my 15-year-old Golf, there wasn't software running on silicon to control the engine.
So I didn't have to worry that the software could be like that in the Toyotas that may have suffered unintended acceleration. There has been no resolution on whether the software caused the issue. The evidence of software guru Michael Barr was so damning that, while he couldn't say that the software caused the incident, he had the Toyota lawyers worried. Add to this the way in which the opposing legal team were being successful in throwing dust into the eyes of the jury and sowing doubt into their minds, and it is clear why Toyota settled out of court.