The semiconductor industry is ramping up for the wider adoption of 3D ICs, which promise better performance, reduced power, and improved yield. While some aspects of true 3D ICs are still evolving, solutions for testing 3D ICs are ready today. The test strategy for 3D ICs has two goals: improving the pre-packaged test quality and establishing new tests between the stacked dice. We describe a test strategy for 3D ICs based on a plug-and-play architecture that allows die, stack, and partial stack-level tests to use the same test interface, and to retarget die-level tests directly to the selected die within the 3D stack.
The fundamental requirements of a test strategy for 3D ICs are the same as for traditional ICs—portability, flexibility, and thoroughness. Therefore, we use an IEEE 1149.1 (JTAG) compliant TAP as the interface at every die and IEEE P1687 (IJTAG) networks and definition for test access. The test interface at each die is based on an IEEE 1149.1-compliant TAP because this is the most common standard device DFT interface. The same TAP structure is used on all dice, so that when doing wafer test on individual dice, even packaged dice, the test interface is through the same TAP without any modifications.
Could the Little ESL Company be the Next Synopsys?
Back in the 1980s, chips were designed with schematics. There was a comprehensive design tool flow to support schematic-based methodology, and the world had three big EDA companies - Daisy, Mentor, and Valid - whom most folks simply referred to as “DMV”. Those three companies thrived on the tools that defined that schematic-based flow - schematic capture, gate-level simulation, timing analysis, place-and-route, and design-rule checking. Life was good, the world was stable, and folks made some decent chips.
Unfortunately, Moore’s Law kept going. Designs got bigger and schematics got unwieldy. We needed a new thing, and that new thing was language-based design.
While DMV were off trying to invent the next generation of schematic-based tools, a new company called Synopsys brought logic synthesis technology out of the lab and commercialized it. That product, Design Compiler, revolutionized chip design by raising the fundamental design abstraction level. It also shook the EDA industry at its roots. By the time the dust settled, we still had a “big 3” EDA landscape, but now the players were Synopsys, Mentor, and Cadence.
Every Little Improvement Counts
I’ve always found ISSCC to be a useful exercise. If nothing else, it puts me in my place if I ever start thinking I know a lot. ISSCC reminds you how little you know compared to the hordes surrounding you. It’s an exercise involving me desperately trying to keep the tip of my nose above water while the presenters all around me make waves.
The available topics vary widely, with some remaining consistent over the years and others coming and going. Energy Harvesting now has its own session, and I spent some time there experimenting with how well I could track the presentations.
So this is for those of you following the low-level things that are gradually making harvesters more efficient and useful. We’ll cover three specific threads: DC-DC converters, multi-source harvesters, and maximum-power-point tracking (MPPT).
Uniquify and the Bitcoin Boom
Get out your pickaxes, canaries, and a high-powered ASIC or two - we're going mining! In this week's Fish Fry, we venture deep into the Bitcoin caves with Bob Smith (VP - Uniquify). Bob and I chat about how the Bitcoin mining race is heating up (literally) and how Uniquify is using their ASIC expertise to create super-powered machines mining today's hottest (and most controversial) virtual commodity. Also this week, I unveil a new unique Amelia-alternative to the current hardware-biased Bitcoin race. I've got two words for you: Bitcoin MMORPG. So strap on your headlamps ladies and gentlemen, we're going in.
450mm Wafers are Still Some Way Away
Years ago I saw a television wildlife programme about penguins. One image that has remained in my mind was that of the hungry penguins clustering on the edge of the ice, needing to go to catch fish, but each frightened to be the first in, as there might be an equally hungry leopard seal wanting a meal of penguin. Eventually, a penguin gets pushed in by his friends. If he survives, the rest then jump in after him.
This image has always recurred to me as chip manufacturers approach the next wafer size increase. They all want to get the benefits of a larger size wafer, but they are frightened to be the first to use the new equipment that will be needed. Eventually, someone makes the leap, and then the rest pour in.
Rolling the Dice and Spinning the Wheel
Take two steps forward and three steps back. Not all parts of our design process are created equal. In this week's Fish Fry, we examine one of the most painful, frightening, and frustrating parts of our design process - verification. My first guest is Tom Anderson (Breker Verification Systems), and we chat about formal verification, what Breker’s new verification technology TrekSoC-Si is all about, and where you can the best vinyl in Silicon Valley. Then, continuing the formal V theme - we go to Vigyan Singhal, CEO of Oski Technology. Vigyan and I dive into the details of the "Decoding Formal Club." The first rule of "Decoding Formal Club"? Well, we're gonna break that one right here. Vigyan also reveals the secret behind the name "Oski". Also this week, I investigate how Netflix is looking to read your thoughts with a little help from Amazon's Cloud services. Better put on that foil hat!
An Anti-Engineering Concept
Synopsys recently announced the results of a flow collaboration with Fujitsu. Modestly buried in the discussion was a mention of 33% improvement in logic per area.
We’ve been at this game for a long time, and you’d think that the low-hanging fruit had long ago been picked. Which would leave us with the occasional 5-10% improvement in this and that after lots of algorithmic tweakage.
And yet here we are, in 2014, with a 33% improvement. Maybe I’m naïve, but that seems significant.
More Than Superconductors?
Last year, I delved a little into the world of superconductors and their bizarre circuits. In poking about afterwards, I ran across something called an “ultraconductor.” I wondered if this was a brand of superconductor – it wasn’t. So what is this thing?
Turns out, it’s not just one thing. I found two threads to pull, and they were different. One led to an organic approach – which would sound pretty danged interesting – but it is not being actively pursued at the moment. (I’m not sure why; for now it’s an academic question, and I’ll tackle it if we ever come back to it.)
The other thread related to some work done at the Los Alamos National Labs (LANL). One Dr. James Maxwell was leading a project to improve conductance beyond what metal alloys could provide.
Microsemi Inserts Man-in-the-Middle to Encrypt Boot-up
Security wonks talk about the “root of trust” for computer systems, and for good reason. If you can’t start from a known-good position, everything that happens afterwards is potentially suspect. Building castles on sand, and all that.
Since every computer and embedded system has to bootstrap itself from cold metal, the boot-up process is necessarily the root of all subsequent trust. If the boot ROM is compromised… well, there’s no telling what mischief may follow.
That’s the concept behind Microsemi’s new “secure boot reference design.” Lock down the bootstrapping process first, and you can then start building a secure system on top of it. A lot of companies have made token efforts to secure their respective processors’ firmware.
Cadence Acquires Forte High-Level Synthesis
High-level synthesis has always been the “personal jet pack” of electronic design automation. We all know that someday, “in the future,” we won’t need all these cars and roads and stuff. We’ll each have our own personal jet pack to take us quickly and directly wherever we want to go. And, when we get there, we’ll do all of our electronic designs in abstract, powerful, high-level languages and synthesize them with high-level synthesis (HLS) technology. Hunger and war will be things of the past, disease will no longer exist, and billion gate semiconductor designs will be automagically conjured up from a few simple lines of easy-to-understand algorithmic code.
Timing analysis and RTL debugging? Bah! Those will be problems of the past - like repairing broken wagon wheels. In the future, our designs will be correct-by-construction masterpieces,