The Process of Process Tracking
Satin Attempts to Corral a Recalcitrant Beast
Want to scare an engineer? There’s an easy weapon out there. And it consists of only one word.
“Process.”
Process is supposed to mean that a company has a formula, that they have a way of doing things that works, and that it’s repeatable, and – most importantly – that it’s a feature of the company, not some individual that works there. That means the process survives even when key people are no longer working there.
Springtime in the SoC
Audio IP, Static Analysis and Board Member Switch-a-roo
In honor of the Design Automation Conference that is less than a month away, I take a little foray into the mysterious land of tools. First up, I chat with Henk Hamoen (Synopsys) about how Synopsys is working its way into audio IP, and then it's an interview with Mark Zarins of GrammaTech about static code analysis and why your level of comfort in dealing with abstraction is important to them. Finally, I have a special “News You May Have Missed" segment about some recent rumblings on the Mentor Graphics Board of Directors.
Also this week, I have a brand new nerdy giveaway (a TI MSP-EXP430FR5739 Experimenter Board) courtesy of Mouser to throw your way, but you'll have to tune in to find out how to win.
An EDA Foil Hat
iROC Attacks Cosmic Attacks
We are all under attack. Don’t bother hiding the kids; there is no escape. Well, not much, anyway. A foil hat won’t be enough to protect them, and they’d be totally abused at school in a full-body foil outfit.
This constant bombardment isn’t news; it’s the familiar neutron (amongst other particles) assault that comes from space or the materials around us. And it’s just waiting to mess up the system you designed.
Power When You Need It
Aldec Harnesses Massive Server Capacity
Warning! We are going to say the “C” word in this article. If you can’t take it, just stop reading now and save yourself a lot of heartache and grief. We know a lot of you are sensitive on this topic and have deep-rooted emotional issues about it. Our advice is to seek professional counseling.
For those of you who are less delicate (we assume you’re still reading), we proudly present a system that has the potential to accelerate your design verification efforts beyond anything you could currently achieve. You know how it goes. You do your initial debugging just fine with your local copy of your favorite HDL simulator, but then you reach a point in your project where you need to crank some serious vectors through that bad boy. That’s when it gets tricky.
True 3D MEMS
Work at MIT Takes MEMS beyond Quasi-3D
Everyone is jumping on the 3D bandwagon. But if I said that MEMS was just taking some steps in that direction, you might understandably question my mental health, since, at first blush, it would seem that MEMS structures are already 3D.
After all, that most primitive MEMS element, the cantilever, to name one example, is specifically intended to move out of the wafer plane – why is that not 3D?
Verifying Today’s SoCs Requires a New Approach
As is well known, the system-on-chip (SoC) verification problem grows faster than design size, so it takes more time and effort to verify a complete SoC than an individual IP block. However, the problems with SoC verification are deeper than just the increase in size.
The biggest new wrinkle introduced by today’s large multicore SoC is the greater number of shared resources, sometimes called “points of convergence” by verification engineers.
I Can Has Roadmap?
The Common Platform Alliance Goes to 14 nm and Beyond
It’s a fine marketing line: pick a strong, simple message and reinforce it without smashing it into your prospect’s face. You want to direct someone’s actions without them feeling like they’re being directed.
Most conferences have a cacophony of messages. I’ve been asked many times, “What are you seeing at [name your conference here]?” and I’m sometimes stumped for an answer because I’m seeing so many different things. Of course, most conferences are put on by organizations whose stake is simply in putting on a conference, so the messages really come from the exhibitors or presenters, and attempts by the organizer to unify a theme seem lackluster at best.
Revitalizing the Chip Startup Environment
Revitalizing the Chip Startup Environment One of today’s biggest Silicon Valley gripes is the evaporation of venture capital (VC) funding for chip startups. Since the dotcom bust, consumer application-driven silicon innovation has been reduced to a relentless chase after Moore’s Law – improving power, cost and speed for incremental multimedia and wireless enhancements in a race down the consumer product generational roadmap to Inventiveness Oblivion.
With 40+ years combined founding and joining startups and working for giant chip and systems companies, the authors have seen Valley booms and “game changer” technologies come and go. Now, though, industry veterans feel Silicon Valley isn’t re-evolving, but dying.
A Dinosaur is Leaving Footprints in Your Smartphone
The old playground joke was, “How do you know when an elephant is in your refrigerator?” Answer: “Footprints in the butter.” Now British company, eoSemi, is asking a more serious question: “How do you know that there is a dinosaur in your smartphone?” “Footprints in the PCB.” This isn't Jurassic Park, so eoSemi’s dinosaur is the quartz crystal oscillator that is vital to the operation of the ever more complex smartphones and tablets.
Staring Down Giants
Achronix Introduces New 22nm FPGAs
It takes a lot of guts to go head to head with an established industry leader. It takes even more guts to go up against an established duopoly - directly in their most heavily fortified markets. Fighting against one giant is tricky. You have to look carefully to find a vulnerable spot and put all your energy into exploiting that vulnerability. Fighting against two different giants is a whole 'nother ballgame. What works against one opponent may not work against the other - and giants tend to be big and heavy. You don't want to get squished between them.