FPGA Power Management and Modeling Techniques
This white paper discusses the major challenges associated with accurately predicting power consumption in FPGAs, namely, obtaining accurate signal activities, static power modeling, and dynamic power modeling, as well as how Altera addresses these challenges through the PowerPlay early power estimator and the Quartus® II PowerPlay power analyzer. This paper also presents the accuracy of the model by comparing predicted power consumption with actual silicon measurements using an extensive suite of real-world customer designs. Using these best-in-class power analysis tools, a designer can model the power consumption of their design to within, on average, ±10% accuracy when used with accurate design information.
White Paper sponsored by Altera
Digital Predistortion for Base Station Power Amplifiers
In this episode of our new Chalk TalkHD series, Amelia Dalton talks to Todd Nelson from Linear Technology about how digital predistortion (DPD) can be used to save millions of dollars worth of power in base station designs. DPD is simple to apply, and has a dramatic impact on the power amplifier - the most power-hungry part of modern base stations. In this Chalk TalkHD you'll hear how DPD works and how you can apply it to your next design.
Chalk Talk sponsored by Linear Technology
PDN Design and FPGA Transceiver Performance
PDN designs targeting transceiver (SERDES) FPGAs require clean voltage sources with strict voltage rail requirements. This document describes the advantages of modern switching voltage regulators in a power distribution network (PDN) design to achieve the best FPGA transceiver performance. This white paper provides guidance on voltage regulator selection for low-noise applications, and a test case that demonstrates the transceiver performance for different types of voltage regulators and voltage rail configurations.
White Paper sponsored by Altera
A Review of BCDlite
GLOBALFOUNDRIES offers BCDliteTM foundry technology optimized for applications such as power management devices, audio amplifiers, displays and LED driver integrated circuits (ICs).
Data Sheet sponsored by ARM
Integrated Power and System Management
In this episode of Chalk TalkHD Amelia chats with Shyam Chandra of Lattice Semiconductor about an integrated approach to system and power management that will lighten your design load, improve your overall system design, and probably lower your total cost at the same time.
Chalk Talk sponsored by Lattice
Meeting the Low Power Imperative at 28 nm (REVISED)
Reducing power consumption in electronic products is no longer just a good idea; for many product developers and manufacturers, it is an essential strategy for gaining competitive advantage in an increasingly power-aware and power-hungry world.
White Paper sponsored by Altera
Power Manager Pickle Power
This video is on the lighter side of Lattice. The Power Manager II family of devices integrates common, and some not-so-common, board power management functions into a single chip at half the cost.
Reducing Power Consumption and Increasing Bandwidth on 28nm FPGAs
Lower power consumption and higher bandwidth are now the two dominant requirements in designing next-generation high-end applications. The global trend across multiple markets is for higher bandwidth in the same footprint at the same or lower power and cost. The Internet is going mobile and video is driving bandwidth requirements at a growth rate of 50% year on year. The march to 40G and 100G systems (with 400G on the horizon) is underway to support this ever-growing bandwidth demand. Fierce competition is driving down prices. Space constraints abound, and cooling solutions often dominate the power budget, sometimes up to twice the power consumption of the electronics. The next generation of 28-nm high-end Altera® FPGAs addresses these challenges through leading-edge technological innovation, integration, and reduced power consumption.
White Paper sponsored by Altera
Power Supply Transients on RTAX-S and RTSX-SU Devices
Single-event effects (SEE) during operation of power regulators can cause the output of the regulator to be as high as the regulator input for short durations, on order of tenths of microseconds. Consequently, any device that is powered by the regulator could see this supply glitch during normal operation of the device. This report summarizes the experiments and data collected to study the impact of these power supply glitches on the RTAX™-S and RTSX-SU devices on printed circuit boards.
White Paper sponsored by Microsemi
Power Estimation and Management for MachXO2 Devices
A key requirement for many of today’s high volume FPGA applications is low power consumption. The MachXO2™ PLD provides many power-saving features including Power Controller, Bank Controller and Power Guard. This technical note provides users with detail for using the MachXO2 low power architectural features including power supply considerations and power estimations provided by the Power Calculator tool.
Reducing Power Consumption and Increasing Bandwidth on 28-nm FPGAs
Lower power consumption and higher bandwidth are the dominant requirements in designing next-generation high-end applications. The trend is for higher bandwidth in the same footprint at the same or lower power and cost as the Internet goes mobile. The march to 40G and 100G systems is underway to support this ever-growing bandwidth demand. Fierce competition is driving down prices. Space constraints abound, and cooling solutions often dominate the power budget, sometimes up to twice the power consumption of the electronics. Altera’s 28-nm FPGAs address these challenges through leading-edge technological innovation, integration, and reduced power consumption.
White Paper sponsored by Altera
Power Supply Management in High-Availability Systems
One of the most basic (and most often overlooked) aspects of high-reliability system design is getting reliable power to all of our components. We need the right kind of power at the right places - at the right times, and in the right order. We need to handle power-up, power-down, and reset cases (among others). It can be really complicated. In this episode of Chalk TalkHD, Amelia Dalton chats with Wendy Lockhart of Microsemi about how to handle power management for high-reliability systems.
Chalk Talk sponsored by Microsemi
Designing for Low Power
FPGAs are becoming one of the most important facets of basestation architectures, and so the spotlight has fallen on them to minimize power consumption. To minimize power consumption the LatticeECP3 FPGA family uses variable channel lengths, optimized low-power transistors, and improved routing defaults and algorithms. As a result, the ECP3’s static power consumption was reduced by 80% and total power consumption by over 50% for typical designs, compared to competitive SERDES-capable FPGAs.
White Paper sponsored by Lattice
The Power Management IC for the Intel® AtomTM Processor E6xx Series and Intel® Platform Controller Hub EG20T
Time to market, cost, board size constraints, reliability and design capabilities are among the motivating factors in choosing Power Management IC versus a discrete solution. However, a discrete solution allows design optimization, offers higher power efficiency, flexibility and is easy to debug. Often, it is not possible to determine which choice will be better without understanding the details of design requirement. This paper aims to discuss both the advantages and disadvantages of using Power Management IC versus a discrete solution on the Intel® AtomTM Processor E6xx series platform.
White Paper sponsored by Arrow
Intelligent Power Management with SmartFusion Intelligent Mixed Signal FPGA
The Mixed Signal Power Manager (MPM) reference design delivers flexible power management configured using the standalone MPM PC GUI tool to bear on power sequencing and management.