Implementing FPGA Design with OpenCL – A Future Look
Are you using FPGAs to accelerate your system? Altera is exploring a new technology for FPGAs that will provide exciting and significant productivity gains for your high-performance systems. Watch this webcast to find out about Altera’s Open Computing Language (OpenCL™) program for FPGAs.
White Paper sponsored by Altera
Optimizing Performance, Power, and Area in SoC Designs Using MIPS® Multi-threaded Processors
Hardware-based multi-threading technology has for some time been known in the industry as a feasible technique for improving system performance, but not too many people are aware of just how much traction the technology has gained since its early implementations in the 1960s. This article provides a brief history of hardware based multi-threading and some examples of its commercial adoption so far. It then gives an overview of the fundamental value of multi-threading in hardware, and describes MIPS Technologies’ multi-threading architecture and product offerings. The article also provides several multi-threaded application examples—including those in the areas of driver assistance systems and home gateways—to demonstrate the broad applicability of multi-threading in real-world applications.
White Paper sponsored by MIPS
Understanding the Impact of Single Event Effects in Networking Applications
Reliability of communication is essential in networking applications. The goal of five nines (99.999%) in network availability translates to less than six minutes in downtime in a year for the entire network. Among the many impacts on system reliability are the effects of ionizing radiation on electronic circuits. This radiation can cause memory elements in electronic circuits to change state. When this happens in the configuration memory of SRAM-based FPGAs, it can cause a change in the functionality of the circuit, greatly impacting system reliability. Designers of networking applications must understand the effect of this radiation and how to reduce the risk to the network.
White Paper sponsored by Microsemi
Preparing for Google TV
Google and partners recently announced Google TV—an open, architecture-neutral platform that will bring the full web experience to television viewing. Given the fact that MIPS licensees lead in the digital home today, it is likely that there will be a large number of future Google TV systems based on the MIPS architecture. Leveraging our work with Android and our ongoing relationship with Google, MIPS is in an excellent position to work with our licensees as Google TV moves beyond initial reference platforms and into mainstream development within the digital home market. By designing your SoC to the right specifications now, you can be ahead of the market when the Google TV code is available in open source in 2011. In this paper, we will provide you with an in-depth description of hardware requirements and recommendations for developing an SoC that will support the Google TV operating system!
White Paper sponsored by MIPS
Debugging Machine Check Exceptions on Embedded IA Platforms
Embedded systems must be able to detect, recover from and report errors. This is a critical feature during debugging and also for quality control after product manufacturing has commenced. Advanced error handling is especially important for embedded systems. This white paper presents a step-by-step approach to debugging machine check exceptions and understanding their causes are resolving errors in embedded Intel® architecture platforms.
White Paper sponsored by Intel
PowerPC to MIPS® Architecture Migration Guide (REVISED)
Software investment is the biggest ticket item in any project. Hence it is important to choose an instruction set architecture (ISA) that offers a truly scalable solution for future development. To address various embedded market segments, MIPS Technologies offers distinct, binary-compatible families of processor cores that span applications from 32-bit microcontrollers all the way to 64-bit multi-threaded, superscalar many-core processors for networking infrastructure, and numerous digital consumer markets in between. Since one can seamlessly scale the performance range between a wide array of processors, the MIPS® architecture offers an ideal path for protecting software investment on a new design or a follow-on/upgrade to an existing project. This paper illustrates the ease of migration from the Power to MIPS architecture, and highlights the areas that users need to focus on during this process.
White Paper sponsored by MIPS
Beyond the Hype: MIPS® - the Processor for MCUs
A market leader in the Digital Home and Networking sectors, MIPS has adapted its industry-standard MIPS32® architecture to address the requirements of 32-bit microcontroller (MCU) product development, offering a higher-performance, more feature-rich and lower-power solution than that offered by competing cores based on the ARM® architecture. This paper outlines the design features that are implemented in MIPS® processor cores that contribute to their industry-leading performance. Additionally, we compare and contrast MCU design solutions based on the MIPS and ARM architectures. We will provide you with the substance beyond the hype, and key considerations for choosing a MIPS processor core.
White Paper sponsored by MIPS
Streamline Your Video Processing Apps with Design Examples
Wouldn’t it be great if you could develop your video processing applications faster? You can with a complete suite of ready-to-use video processing functions. These functions are ready to be dropped into your design and connected through open Avalon® Streaming interfaces. Watch this 5-minute video for a demo that shows you a low-cost touch screen-based development kit running two design examples based on these functions.
Truth in Randomness
Most engineers will be able to get through an entire career without having to think about the mathematical realities that underlie the principles of randomness and entropy—even though many use or design applications that rely on them to ensure the security of their interactions. For the most part, engineers simply take the vendor’s specifications at face value when incorporating the cryptography hardware (and the code that supports it) into designs. Unfortunately, some recent discoveries about the more subtle and not-well-documented characteristics of random noise sources have shown that you may not be getting all the security you paid for.
White Paper sponsored by Microsemi
Developing Software for Embedded Systems on FPGAs
FPGAs are becoming more common in embedded design. See how easy it is to develop embedded system software for FPGAs using the popular Nios® II soft processor. In this 5-minute video you'll learn about the software development flow for the Nios II processor and see the Nios II Embedded Evaluation Kit, Cyclone® II Edition, in action. You'll also see a graphic demo showing the high performance of the Nios II processor with hardware accelerators.
Implementing Video Display Interfaces Using MachXO2 PLDs
Lattice Semiconductor has developed and supported a number of reference designs for display interfaces in various devices. A display interface is now available in the MachXO2 PLD family. Because this interface is now supported in MachXO2 devices, designers have an even lower cost and very low power alternative to implement embedded displays. As described in this white paper, the MachXO2 provides a compelling choice for this application.
White Paper sponsored by Lattice
User-Customizable ARM-Based SoC FPGAs for Next-Generation Embedded Systems
This white paper discusses Altera’s programmable system-on-chip (SoC) approach to ARM-based embedded system implementation. The single-chip approach can be of particular value to embedded systems developers facing stringent time-to-market, cost, performance, design reuse, and longevity requirements.
White Paper sponsored by Altera
Compiling, Installing, and Running MIPS NDK Native Applications
Are you working on Android apps development? This app note on the MIPS NDK describes how to build Android applications in native C or C++.
Adding Wi-Fi to Your FPGA Design
In the first episode of our new Chalk TalkHD series, Amelia Dalton talks to Bob Potock from Altium as they add Wi-Fi to an FPGA-based embedded system.
Chalk Talk sponsored by Altium
Processor IP Checklist
With their associated software-development tools, simulation models, and EDA flow scripts, processor and DSP IP blocks affect more than just the hardware design; their influence permeates the entire SOC design project. Here is a list of questions to ask yourself, your team, and any processor IP providers you contact. This list will help you to avoid unhappy IP choices and will help you get exactly what your team needs to develop successful SOC designs on time, within budget, and with minimal hassle.
White Paper sponsored by Tensilica