Applying the Benefits of Network on a Chip Architecture to FPGA System Design
NoC interconnect architectures provide a number of significant advantages over traditional, non-NoC interconnects, such as allowing independent layer design and optimization. Altera's Qsys system integration tool, included with the Quartus® II software, generates a flexible FPGA-optimized NoC implementation automatically, based on the requirements of the application.
White Paper sponsored by Altera
An Independent Analysis of Altera's FPGA Floating-Point DSP Design Flow
BDTI performed an independent analysis of Altera’s floating-point DSP design flow. BDTI’s objective was to assess the performance that can be obtained on Altera FPGAs for demanding floating-point DSP applications, and to evaluate the ease-of-use of Altera’s floating-point DSP design flow. This paper presents BDTI’s findings, along with background and methodology details.
White Paper sponsored by Altera
Reliable Reset Generation for TI DSP Processors
Every requires a reset generator circuit or IC to start up from a fixed condition after the supplies are turned on, and prevent the processor from executing instructions incorrectly and causing flash memory corruption. Traditional, simple, single-supply reset generators were adequate for single supply processors, but no longer are sufficient to guarantee reliable operation of multiple supply processors. This white paper examines some of the challenges associated with resetting modern processors.
White Paper sponsored by Lattice
Scalable Smart Debugging With ZeBu-Server
In this episode of Chalk TalkHD, Amelia chats with Lauro Rizzatti of EVE about how EVE's ZeBu emulation technology can help you find that one last bug in even the biggest of designs.
Chalk Talk sponsored by EvE
Teradici Success Story
Synopsys and Teradici: ASIC Prototyping Made Fast and Efficient with Synplify Premier
White Paper sponsored by Synopsys
Introducing the User-Customizable ARM-Based SoC FPGA
Learn how to reduce system power, system cost, and board size while increasing performance and flexibility. Altera’s ARM-based SoC FPGAs combine the performance benefits and power and cost savings of hard logic, with the flexibility and time-to-market benefits of programmable logic – all in a single device.
Adding Wi-Fi to Your FPGA Design
In the first episode of our new Chalk TalkHD series, Amelia Dalton talks to Bob Potock from Altium as they add Wi-Fi to an FPGA-based embedded system.
Chalk Talk sponsored by Altium
Everything You Wanted to Know About SOC Memory*
More on-chip silicon is devoted to memory than to anything else on a SOC and yet memory is often added as an afterthought. This White Paper discusses the many alternatives for on-chip and off-chip memory usage. It discusses the essentials of SOC memory organizations, on-chip SRAM and DRAM, local memories and caches, on-chip non-volatile memories, and memory controllers for off-chip memory. It covers the difference between 6T and 4T SRAM designs, the system design ramifications of NAND and NOR Flash ROM, and how DDR2 and DDR3 SDRAMS compare.
White Paper sponsored by Tensilica
Spartan-6 FPGAs in Video Designs
In this episode of Chalk TalkHD, Amelia chats with Tom Hill and Maureen Smerdon of Xilinx about how Spartan-6 FPGAs can accelerate your next video design, and how adding embedded vision to those designs is getting easier and easier.
Chalk Talk sponsored by Xilinx
Choice of an ISA for Embedded Designs
Software investment is the biggest ticket item in any project. Hence the choice of an ISA that offers a scalable solution is an important consideration. MIPS and our SoC eco system offer distinct families of processor cores that span from 32-bit micro controllers all the way to 64-bit multi-threaded super-scalar cores from single-core to many cores, to address various segments of the embedded markets. For either a new design or a follow on or upgrade to an existing design, the choice of MIPS as the ISA offers an ideal path for protecting the software investment on a project, since one can scale the application up and down the performance scale seamlessly between a wide range of processors. The bulk of the effort in the migration to any new ISA is in the low-level initialization software. This paper illustrates the ease of migration from the ARM to MIPS architecture and highlight the areas that users need to focus on.
White Paper sponsored by MIPS
ZeBu™: A Unified Verification Approach for Hardware Designers and Embedded Software Developers
Moore’s law continues to drive both chip complexity and performance to new highs every year, and continues to stress and periodically “break” existing design flows. Fortunately for EDA users, the same shrinking geometries that make their design problems tougher are also helping to improve the performance for their EDA tools.
White Paper sponsored by EvE
Catapult C Synthesis Designing a JPEG Compression Engine
Amelia Dalton finds out that designing hardware with high-level languages can be both easy and fun as she and Stuart Clubb of Mentor Graphics walk you through the design of a hardware JPEG encoder using C++.
Chalk Talk sponsored by Mentor Graphics
High-Reliability in FPGA Design - SEU Mitigation
Neutrons are coming for you and you'd better be prepared. Whether we like it or not, SEUs (Single Event Upsets) are becoming a bigger and bigger problem for our designs, especially for high realibility systems. If you thought SEUs couldn't mess up your next design because you aren't designing something destined for space, you need to think again. In this episode of Chalk TalkHD, I chat with Jeff Garrison of Synopsys about the how we can battle SEUs (on the ground or in the air) with the latest generation of design tools.
Chalk Talk sponsored by Synopsys
System-Level Debugging and Monitoring of FPGA Designs
This white paper describes the latest state-of-the-art methods for debugging and monitoring large FPGA designs both during the simulation phase of development and after device configuration, and details the current practices that Altera has identified across a representative number of customer designs.
White Paper sponsored by Altera
Strategic Considerations for Emerging SoC FPGAs (REVISED)
Semiconductor devices that integrate FPGA fabric, hardened CPU subsystems, and other hardened IP—SoC FPGAs—have reached a tipping point that will lead to their broad proliferation in the next decade, therefore offering many options for system designers. These SoC FPGAs complement the decade-long availability of soft-core CPUs and other soft IP for building systems on FPGAs. This white paper describes the emergence of system on a chip (SoC) FPGAs, the drivers behind that emergence, and strategic considerations for executive management and system designers when choosing these devices.
White Paper sponsored by Altera