A Horse of a Different Color

Advanced vs. Established Process Geometries

by Amelia Dalton

It's time to saddle up and ride into the semiconductor sunset! Whether you're hitchin' your wagon to a young whipper-snapper node, or lassoin' a long-in-the-tooth workhorse process, the time it takes to get your IC design up and out of the corral may depend more on the software you use to verify your design than on the silicon itself. In this week's Fish Fry, Mary Ann White (Synopsys) and I get down to the very heart of semiconductor design: process geometries. We have ourselves a good ol' time chatting about challenges of FinFET designs, the tricky bits of working with both advanced and established process nodes, and how the right tools can make all the difference when it comes to winning the big product-to-market rodeo.

 

The Next Moore’s Law

What if it Happened Again?

by Kevin Morris

We sit here in our dazed, progress-drunk technology buzz looking back at the half-century rocket ride that transformed not only our industry and engineering profession, but also all of modern civilization. Nothing in recorded history has had as much impact on the world as Moore’s Law. It has re-shaped global culture, dramatically altered politics, and even affected fundamental aspects of the ways human beings work, think, feel, and relate to each other. If this weren’t the single biggest change driver in the history of civilization, it was right up there with democracy, monotheism, combining caramel and chocolate, and some other really heavy-hitters. Innovation in electronics has spilled over into just about every other aspect of our collective lives, and the change is profound.

But, what if it happened again - not in electronics this time, but somewhere else?

To answer that question, we should look at what caused Moore’s Law in the first place. It was a single innovation, really. Just one idea.

 

The Sun Sets on Moore’s Law

Are FPGAs Harbingers of a New Era?

by Kevin Morris

The title may have put you off. In fact, it probably should have. After all, most of us in the press/analyst community have - at one time or another during the past decade or two - been walking around like idiots wearing sandwich signs saying, “The End is Nigh!” And, we got just about as much attention as we deserved. “Yawn, very interesting, press and analysts, and now back to planning the next process node…”

It gets worse. Predicting that Moore’s Law will end is pretty much a no-brainer. It’s about as controversial as predicting that a person will die… someday. There is obviously some point at which the laws of physics and the reality of economics will no longer allow us to double the amount of stuff we put on a single chip every two years. The question is - when will we reach that point, and how will we know we are there?

 

Multi-Patterning Rollout

What’s Coming When?

by Bryon Moyer

As we continue to try (and succeed at) stuffing more circuity into a tiny space than physics allows without great cleverness, we are drifting more and more into the use of multiple patterning. We’ve looked at this a number of times, starting with the simplistic view of litho-etch-litho-etch (LELE) approach and then digging deep into the far less intuitive self-aligned (or spacer-assisted) double-patterning (SADP).

As we’ve mentioned here and there, these technologies are, to some extent, in production – and more is coming. What’s a bit confusing is what’s coming when and why. Today’s musings attempt to sort that out.

But before we do that, let’s do a quick review (with more details available in the prior pieces linked above). Multiple patterning is a trick we play so that we can place features closer together than can be done with a single exposure. The solution? Split the mask pattern in half and do two exposures.

 

From the Cradle to the Cloud

Education Meets High Tech

by Amelia Dalton

This week Fish Fry is all about technological innovation in education. From kindergarten to college, from Malaysia to Texas, we look into recent technological advances that aim to even the educational playing field in the United States and across the globe. My first guest is Scott McDonald (Rorke Global Solutions). Scott unveils Rorke’s new digital learning system and discusses with me how Rorke was motivated to break ground on this high tech education revolution. (We also throw in some basketball trash talk.) Keeping with our education theme, Silicon Cloud International CEO Mojy Chian joins Fish Fry to explore the future of cloud computing and how Silicon Cloud International's educational cloud centers hope to create a whole new generation of chip designers.

 

FPGA-Prototyping Simplified

Cadence Rolls New Protium Platform

by Kevin Morris

System on Chip (SoC) design today is an incredibly complicated collaborative endeavor. By applying the label “System” to the chips we design, we enter a realm of complex, interdisciplinary interactions that span realms like analog, digital, communications, semiconductor process, and - with increasing dominance - software. Since the first SoCs rolled out a mere decade or so ago, the composition of design teams has shifted notably, with the percentage of cubicles occupied by software developers increasing much more rapidly than those of any of the other engineering disciplines. In most SoC projects today, software development is the critical path, and the other components of the project are merely speed bumps in the software development spiral.

 

Analog Breakthrough?

Pulsic Automates Analog Layout

by Bryon Moyer

You are now entering the “It can’t be done” zone. But, at least for the moment, I’ll ask that you relax that axiom, even if only slightly, to something less absolute, like “We’re pretty sure it can’t be done.”

That’s because we are approaching the Holy of Holies, Mystery of Mysteries, Most Unapproachable of That Which is Unapproachable: analog design automation.

Before we dive in, let’s set up the contrasts first by revisiting the highly automated world of digital design. Heck, digital designers practically don’t need to know what a transistor looks like. They can specify their logic in text format, send that into a toolchain, and voilà: a completed layout.

 

Testing Big-Ass Transistors

Mentor’s Power Tester Accelerates Diagnosis

by Kevin Morris

We talk a lot about transistors in these pages. But usually our discussions center around billions of microscopic transistors acting in concert. This article is not about those. Today, we are going to discuss transistors (and diodes and other components) about the size of your smartphone. These BATs (or “IGBTs” - Insulated-Gate Bipolar Transistors), as the industry seems to insist on calling them) are used in power electronics applications - like electric and hybrid cars, wind and solar power, and that amplifier the kid across the street is building in his basement (the one you’ll be able to hear two states away).

Typically, devices in these high-power applications are subjected to large thermal loads and repeated heating/cooling cycles. Also typically, we want them to last a long time. Nobody wants to be climbing up wind turbines every few months to replace power electronic components. Unfortunately, these repeated thermal cycles cause expansion and contraction, which puts mechanical stresses on the components, the substrates, and the connections. When we design a system, we want to have a pretty good idea how well and how long our components will operate - under the conditions we are expecting in our application.

 

Is the Classic Design Chain Broken?

Or Is It Just Another Step in Evolution?

by Dick Selwood

It used to be so simple. A group of chip designers would sit around drinking coffee and gently mulling things over when one would say, "You know what would be really cool? If we add a backward splurge feature to the K11 widget, it would allow users to do some awesome things."

After a bit of engineering discussion, the sales team would go off and chat to a few friendly customers, come back and say, "They aren't against it." After this, management would buy into the project. When the device was launched, the marketing team would make a lot of noise about user input and then the company would sit back and wait for orders. Sometimes they came, sometimes they didn't.

 

Challenged By FinFETs

Ansys’s Latest Redhawk Has to Work Harder

by Bryon Moyer

There’s promise, and then there’s reality.

The promise of FinFETs has been one of higher performance with lower power than would have been possible if we had stayed on the same track as before and tried to keep scaling. This promise seems, more or less, to be realizable as companies start integrating these new devices into their aggressive-node designs.

The accompanying reality, in this case, has to do with all of the other details that you get along with the benefits. In other words, those benefits come at a price – and one of the costs has to do with power noise. Ansys has released a new version of their Redhawk power analysis tool (you may think of them as Apache, but they’re now owned by Ansys), and much of what they’ve done in this version has been due to the needs of designs incorporating FinFETs.

 

Baby Got DAC

The Design Automation Conference Returns to the City by the Bay

by Amelia Dalton

Do you know the way to San Francisco? Do you know the way to rows and rows of obscure interesting and innovative point tools? In this week’s Fish Fry, we examine two sides of the multi-faceted ecosystem that is the Design Automation Conference - EDA and IC. On the EDA side, we chat with Chris Porter and Salem Kapetanovic from IBM about how EDA can leverage the Cloud in a whole new way. On the integrated circuit side of DAC life, we chat with eSilicon CEO Jack Harding about how eSilicon is bringing eCommerce to IC design and why IP MarketPlace should be your next stop on the way to GDS11. Also this week, we unveil Amelia’s top five things you may have missed at DAC. (Spoiler alert: DAC Attendees apparently don’t know how to play Jenga™.)

 

Sub-threshold Design

Ambiq and PsiKick Chart a Challenging Path

by Bryon Moyer

We’ve been turning it down for years.

Energy consumption has gradually grown as a concern, to the point where it’s eclipsed performance as a primary driver for many circuits. To reduce power, you can do one of two things: turn down frequency (for dynamic power) or turn down the supply voltage. We’ve already stopped driving clocks as hard as we used to, what with the shift to multicore for scaling performance. But we’re still turning down the voltage.

The first move, where we took logic from 5 V, where it had been for years, to 3.3 V happened… a long time ago. Some components still use 3.3 V, but the leading-edge stuff is all down in the 1-point-something range. And drifting south.

 

Two by Tools

Virtual Prototyping and DAC 2014 Preview

by Amelia Dalton

In this week’s editorial matrix, Fish Fry has EDA on all sides. In one corner, we have Chuck Alpert (DAC 2014 Technical Program Chair) here to give us the skinny on this year’s Design Automation Conference and Expo. Chuck gives the low down on what kind of cool conference tracks and tutorials are being offered, how you can attend the conference on the cheap, and where the hip and happenin’ parties will be found. Then, keeping with our EDA theme, we also sit down with Tom De Schutter (Synopsys) and discuss the benefits and best practices of virtual prototyping for your next design.

 

EDA for DSA

Not What You’re Expecting

by Bryon Moyer

They’d built up the sheep ranch over several decades. Starting small, they learned through experience how sheep thrive. They gradually diversified, experimenting with different breeds – this one for the smoothest wool, that one for higher quantities of milk to be used for feta and other cheeses – and, over time, they acquired solid confidence in their ability to manage the flocks.

But another similar animal started to gain popularity: goats – in particular for their milk, which they gave up in far greater quantities than sheep do. People often view sheep and goats as variations on a theme, so expanding the ranch to include goats seemed like a no-brainer.

 

Viva Vivado!

Xilinx Tunes-Up Tools

by Kevin Morris

As we enter what will perhaps become the “long tail” of Moore’s Law, the traditional battlefield for FPGA companies is shifting dramatically. For most of the history of FPGAs, the main strategic goal was to be “first” on each new process node. If you had FPGAs ready to go on the newest, fastest, densest semiconductor process, you had a significant advantage over your competitor. With each new node, the cost dropped, the power efficiency improved, performance took a leap ahead, and functional density doubled. The combination of those advantages was so substantial that almost nothing your competitor could do would offset a one-node advantage.

Today, however, those new nodes are much harder fought, and the rewards are much more modest. No longer are PPC (performance, power, and cost) automatic “wins” just from moving to the new technology. Leakage current, skyrocketing NRE and mask costs, complex design constraints, and other challenges have forced FPGA companies to make hard compromises among these critical components of semiconductor goodness. Both Xilinx and Altera now have split lines - where “current” devices are not all made on the same process node, and differentiating FPGA product offerings based on process alone has become a losing proposition.

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