New Synopsys SoC Test Features

Cell-Aware: Meet Slack-Based. And STAR: Meet eFlash.

by Bryon Moyer

Ah, the air has cooled. The sun lolls about at a low angle for a few tentative hours. Morning frosts seal the fate of any remaining tender plants. Here in northern Oregon, the Gorge winds blow random gale-force patterns, making it unnecessary to sweep the leaves off of the patio. And, slightly farther north, it’s ITC (that would be the International Test Conference) season, in Seattle this year.

Which means it’s the season for test announcements by EDA companies. Synopsys made some noise, but not with one big blockbuster new thing; rather they assembled a couple of newsy bits that, summed together, merit some discussion.

Just to organize my thinking here, so that I don’t get us lost, there are two basic announcements: Cell-aware+Slack-based testing and STAR for eFLASH. The first involves two subtopics that we should review first.

 

Single-Electron Transistors

A Whole New Way of Switching

by Bryon Moyer

I love surprises like this. You go into what promises to be a wonky, even dull, conference presentation – and come out agog.

That’s exactly what happened to me at the recent ICCAD in San Jose. It was a presentation based on a collaboration between the University of Michigan, Shanghai Jiao Tong University, and National Tsing Hua University about some placement or routing algorithm, but it happened to involve a transistor type that I’d never heard of. And… I don’t know, there was something about the regularity of it, perhaps its elegance, illuminated through a very lucid presentation, that caught my fancy. Heck, even with no prior knowledge, I could actually follow most of the talk. That was exciting enough. Great success!

So… what was this thing? It was a way of implementing logic on a fabric of single-electron transistors (SETs). In fact, a reconfigurable fabric. This could be your new FPGA some years hence. But, while I could follow the logic of the presentation, I had no idea what a SET was, nor did I understand why certain constraints existed that affected the algorithms presented.

 

Plan 8 from Outer Space

Calypto’s Catapult 8 Takes Us Higher

by Amelia Dalton

Bob killed the headlights and put the car in park. We sat in silence. Eerie lights danced on the horizon. First east, then west, and then straight up into the night sky. We watched with mouths agape as the lights came closer (and closer), only to quietly fade away. A UFO in our midst? Not quite. HLS. Most of us have been watching the skies in hopes for the arrival of High Level Synthesis for years. Steering today's HLS-powered flying saucer is my guest Mark Milligan (Calypto Design Systems). Mark is here to reveal the mysteries of Catapult 8. He'll shine a light on how HLS is powering image processing and video applications, and explain how we can get to design closure from the top or the bottom. Also this week, we introduce a kickstarter campaign that aims to bring fashion-forward wearable fitness monitors to your next holiday wish list.

 

Xilinx Divides the World

Separate Flows Target Software and Hardware

by Kevin Morris

The problem... is you.

I know, it seems a bit harsh, blaming FPGA designers for restricting the expansion of the FPGA market. After all, FPGA designers are the fans, right? We are the loyal, the ones who have supported the technology all these decades, the ones who have toiled and struggled and applied our customer-side creativity to help solve the myriad challenges associated with getting one of the coolest and oddest chip architectures ever invented to behave well enough for actual system use.

Exactly.

 

Spaghetti versus ISO 26262

Are You Ready for Tomorrow?

by Dick Selwood

There are times when you shouldn't really think too deeply about things. Last week I was driving along the motorway from London to Winchester. While accelerating to overtake, I saw the engine pass through 4,000 rpm, and I wondered about each piston moving from stationary at top dead centre to stationary at bottom dead centre and then back to top dead centre 50 times a second. (Geeky? Moi?) Sadly, I can't perform in my head the sum that would calculate the speed at which each piston was moving at its fastest, but it must be pretty speedy, and that cycle of movement would be putting all sorts of stresses on all sorts of metal parts. I eased my mental stress by consoling myself that, at least in my 15-year-old Golf, there wasn't software running on silicon to control the engine.

So I didn't have to worry that the software could be like that in the Toyotas that may have suffered unintended acceleration. There has been no resolution on whether the software caused the issue. The evidence of software guru Michael Barr was so damning that, while he couldn't say that the software caused the incident, he had the Toyota lawyers worried. Add to this the way in which the opposing legal team were being successful in throwing dust into the eyes of the jury and sowing doubt into their minds, and it is clear why Toyota settled out of court.

 

Finding the Right Prototype

Carbon Design Systems Announces the Carbon System Exchange

by Bryon Moyer

So I hear you’re going to try to build an SoC. Good luck; you’ve got lots of work ahead.

First you have to come up with an architecture. Then you need to design all of the blocks yourself. Then you need to write all of the software that’s going to run on this beastie. By yourself.

That’s the easy part. When you’re done with that, you have to verify the whole thing. Yes, you have to design everything and finish it all before you can start your verification. I just hope you don’t make any mistakes at the early architecture level.

So, okay then, off you go like a good lad.

 

Over the FR4 and Through the Woods

To Grandma's PCB We Go

by Amelia Dalton

This week’s Fish Fry is all about your next PCB design. From power integrity to mixed-signal place and route, from Gerber files to schematics, from output pins over the FR4 and through the vias, to grandma’s house we go. My first guest this week is Greg Lebsack from Tanner EDA, and we discuss why you want a digital place and route tool, integrating ye ol’ analog into your next design, and what Tanner EDA brings to the mixed-signal party. Next up, we bring in Hemant Shah from Cadence Design Systems to chat about one of the biggest pain points of PCB design: the hand off to manufacturing. Hemant and I investigate a rapidly expanding industry consortium that is hoping to change all of that awful file hand off once and for all.

 

Constraining Light

Or, How the Heck Do I Design a Photonic Circuit?

by Bryon Moyer

Several weeks ago we took a look at the expanding role of EDA. And then a couple weeks ago we delved into the bizarre world of silicon photonics. Yeah, we didn’t get too deep because the bottom drops off pretty quickly, and I’m not sure I could tread water credibly any deeper. But we got a flavor.

So now, we bring these two things together to answer the question, “If I’m going to be involved in a photonic chip design, what tools am I going to use?” OK, so if you’re an electronics designer, you’ll probably be asking the question, “What tools will the photonics pholks be using, and how will thier world interface to mine?”

Folks have been doing silicon photonics research for a long time now, and you need tools to do that. So it’s not like we’re just now seeing the emergence of new tools for this purpose. The thing is, there’s not a lot of profit in research, so the big guys that are commercially driven may not be attracted to such new endeavors in the early stages.

 

First Responder Robots and Virtual Prototypes

Carbon’s New Virtual Prototype Portal and UDG’s New Smart Robot

by Amelia Dalton

What’s the difference between a human and a pile of rocks? A robot algorithm (of course)! In this week’s episode of Fish Fry, we check out a new robot being developed at the University of Guadalajara that utilizes a pattern recognition algorithm to determine the silhouette of a human body. Also this week, we talk about the trials and tribulations of SoC design with Bill Neifert of Carbon Design Systems. Bill and I discuss Carbon's focus on the automatic creation of RTL-accurate models for integration into SoC designs and how you can make your IP configuration options a whole bunch easier.

 

Expanding EDA

Newer Tools Let You Do More than Just Electronics

by Bryon Moyer

Welcome to autumn. It’s usually a busy season – although the activity typically starts more with the onset of September and the resumption of school than with the equinox. But it also comes on the heels of a quiet season, even in the overworked US.

And EDA has seemed moderately quiet. So I started looking around to see what I might have been missing, and I’m not sure there’s a lot. But it did get me musing on why things might be quiet for the moment as well as what fills the gap – which gets to the topic of what qualifies as EDA. It’s more than you might think.

At the risk of being obviously over-simple, the legions of coders in EDA-land are doing one of two things: building new technologies or improving on old ones. The new technology category might include support for FinFETs or multi-patterning or the design kits for the latest silicon node. The improvement side of the tree is where performance and capacity and usability are juiced up – all in the name of productivity, of course.

 

Shifting Left

Designing Code, Breaking Code, and the Verification in Between

by Amelia Dalton

Like the venerable Kenny Rogers once said, “You have to know when to hold ‘em, know when to fold ‘em…” In the verification game, much is the same. You have to know how to make the code, and you have to know how to break it. In this week’s Fish Fry, David Hsu (Synopsys) joins us to discuss the challenges of static verification and formal verification, how to “shift left”, and how to make code just to break it. Also this week, we investigate how hierarchical timing analysis may solve your sign-off timing troubles once and and for all.

 

Go-Fast FPGA Design

Helpful Hot-Rodding Hints

by Kevin Morris

Most of us engineers are at least closet hot-rodders. It’s in our DNA. No matter how good a contraption is from the factory, we just can’t resist the temptation to tweak a few things in our own special way, and often that’s all about speed.

FPGA design, it turns out, is a big ‘ol blank canvas for hot-rodding. Even though we (fortunately) don’t have glossy convenience-store magazines adorned with scantily-clad models standing next to the latest tricked-out dev boards, FPGAs have all the tools we need to rev our creative motors in the never-ending quest for that extra little bit of personalized performance.

But, where do we start? Do FPGAs have a set of go-to hop-ups? Is there a “chopping and channeling” baseline for programmable logic design?

It turns out the answer is “yes.” And, just to get you started, here are five tips for turning up the boost on your next project:

 

Going Vertical

Ecosystem for Interposer-based Design?

by Kevin Morris

We’ve talked a lot lately in these pages about the impending demise of Moore’s Law. Consensus is that, somewhere around the half-century mark, one of the most astounding prophecies in human history will have finally run its course. Next year, we’ll have a round of FinFET devices that will be so exotic and expensive that only a handful of companies will be able to use them. In the decade that follows, we may or may not reach 10nm and 7nm production - using either esoteric unlikelies like EUV or extreme-brute-force multi-patterning techniques - to solve just some of the multitude of barriers to continued downscaling.

Sci-fi techniques like carbon nanotubes, graphene-based devices, quantum computing, and that other-one-you-read-about are so far from production practicality that we may not see any of them in widespread use in our lifetimes. While incredible research shows great promise for many of these ideas, they are all back in the silicon-equivalent of the early 1960s in their evolution. The time and engineering it will take them to catch up with and eventually surpass what we can do with silicon today is substantial.

 

On The Hunt: Part One

HLS and Sub-atomic Particle Jitter

by Amelia Dalton

Dateline: The 5th of September. Time: 2100 hours. We're on the hunt. No, we’re not hunting the mysterious Yeti, the Loch Ness monster, or heck even the ever-elusive EUV. This time, we're looking for some HLS. My guest this week is Mark Milligan from Calypto. Mark joins Fish Fry for the very first time to bring HLS into the light, into the world, and into the caring hands... of Google? Oh yes. Also this week, we delve into the deeply nerdy realm of sub-atomic particle jitter and investigate how the U.S. Department of Energy's Fermi National Accelerator Laboratory is hoping to solve an age-old existential question: How many dimensions do we really live in? (Spoiler alert: The space-time continuum may actually be a quantum system made up of countless tiny bits of information.)

 

Optimization Moves Up a Level

Mentor’s RealTime Designer Rises to RTL

by Bryon Moyer

There are a lot of reasons why we can create so much circuitry on a single piece of silicon. Obvious ones include hard work developing processes that make it theoretically doable. But someone still has to do the design. So if I had to pick one word to describe why we can do this, it would be “abstraction.” And that’s all about the tools.

In fact, my first job out of college came courtesy of abstraction. Prior to that, using programmable logic involved figuring out the behavior you wanted, establishing (and re-establishing) Boolean equations that described the desired behavior, optimizing and minimizing those equations manually, and then figuring out which individual fuses needed to be blown in order to implement those equations. From that fuse map, a programmer (the hardware kind) could configure a device, which you could then use to figure out… that it’s not working quite like you wanted, allowing you to throw the one-time-programmable device away and try again.

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