posted by Bryon Moyer
You’d think a complete new technology for patterning silicon would merit a long, involved story. And yet it’s just not that complicated. (Easy for me to say…) One of the up-and-coming lithography processes under development is called “nanoimprint lithography” (NIL). It might be hard to imagine that this would work, but, just like it sounds, it involves taking a master “stamp” and impressing it into a liquid resist.
You then harden the resist with some exposure to UV light and release the master. The pattern on the wafer can then direct further more standard processing.
The crazy thing about this is that nanometer-scale features can print. You’d think that the liquid might have trouble conforming to such miniscule hollows in the template. And some of the issues you might think could arise – like parts of the pattern slumping or collapsing after the template is removed – truly are issues that are being studied and addressed.
Right now, researchers are working in the 26-nm realm (according to presentations at SPIE Litho), but they are trying to use the same process as HGST used for their hard drive project – creating working templates from a master template. Quality is still a challenge for those working templates, making this most suitable for applications having large-scale repeated features for which redundancy can be provided for repair.
The presenter from Dai Nippon Printing said that full production is targeted for two years out. We’ll continue to track it… If you get the SPIE Litho proceedings, you can find more in paper 8680-2.
posted by Bryon Moyer
DSA – Directed Self Assembly – is 2/3 natural and 1/3 artificial. The “self assembly” part (two of the three words, to make the scoring clear) is a natural phenomenon governing how mutually immiscible materials will resolve their differences in staking out territory.
It’s the “directed” part that makes it a useful tool. We’ve looked before at some basics for controlling how to create lines, for instance. But actual circuit patterns will be more complex, and several SPIE Litho presentations focused on different ways of affecting the outcome of the self-assembly process.
MIT’s Professor Ross, for example, talked about using posts to direct the outcome. To help bias what goes where, they would “functionalize” the posts by “brushing” them with one or the other of the block copolymers, establishing an affinity for one and a “don’t go there” for the other. The big question then becomes, where to place these posts?
Given a set of posts, there are some formidable-sounding techniques for calculating what the impact will be and how the block copolymers will lay out: Self-Consistent Field Theory (or Mean Field Theory) and Dissipative Particle Dynamics, both of which deal with reducing complex fields to particles to simplify the modeling.
But the real question is, if you want a given pattern, how do you go backwards to figure out the positioning and functionalizing of the posts? Apparently, the results aren’t going to be intuitive. For example, if you want to create a T-shaped structure, you need to omit a post from the center. Go figure.
So at this point, it appears there isn’t a deterministic path to calculate where the posts should be; they used a Monte Carlo approach to back into the solution. Which may end up being satisfactory for a while or for small circuits, but for an entire large-scale SoC-scale design, I would assume (and, to be clear, this is conjecture on my part) that some separability would apply such that you could partition the entire thing into smaller solvable regions, but you’d need to be able to deal with the region boundaries to account for their interactions.
The bottom line here is that, as DSA develops into a viable production process, there will be new challenges for EDA folks to help turn circuits into DSA guiding patterns.
If you have the SPIE Litho proceedings, you can find more of the MIT presentation in paper 8680-1.
posted by Jim Turley
San Diego-based Express Logic just received IEC 61508 and IEC 62304 certification for its ThreadX operating system. These two standards cover the "functional safety of electrical, electronic, and programmable electronic safety-related systems." The nice part is, the certification is for bone-standard ThreadX; there is no special "safety-certified" version of the RTOS. Express Logic says it won't even charge more, now that it's certified.