posted by Bryon Moyer
Flash memories degrade over time as the oxide gets damaged and loses its ability to hold charge. It’s apparently well known that this damage can be annealed out, but that takes time and/or temperature. You can’t heat the chip over 400 °C, so you have to anneal for minutes for nominal results.
As described in an IEDM paper, Macronix modified their cell to allow a high current in the vicinity of the cell. By running that current for milliseconds, it could create local heating above 800 °C. This resulted in endurance over 100,000,000 cycles with good retention.
Alongside the MRAM papers, it strikes me as a familiar thing because Crocus also uses a local heater for thermally-assisted switching of their MRAM cells, although the temperatures aren’t nearly as high. I don’t know if this is truly a case of cross-pollination, but it feels like it.
If you have the IEDM proceedings, more detail is available in paper #9.1.
posted by Bryon Moyer
There’s lots of interest in using germanium in pFETs to improve the symmetry between n- and p-channel devices in a CMOS inverter. But integrating it with silicon has been challenging; at the very least, defects at the lattice interfaces have posed a significant barrier to progress.
Amongst the papers at IEDM, a couple featured ways of integrating Ge – literally – and confining defects.
A team from IBM, ST, Globalfoundries, Renesas, and Soitec devised a way of creating a uniform SiGe channel in a PMOS device on an extremely-thin SOI (ETSOI) wafer. This required moving to an isolation-last approach to avoid artifacts at the edges of the p-channel devices that would make performance layout-dependent. Instead, they blanketed the whole wafer with SiGe and selectively etched away the unneeded portions, leaving a layer of SiGe over the Si where the p-type channel was going to be. They then performed a “condensation” step – high-temperature oxidation that pushes the germanium from the SiGe layer into the silicon below it while oxidizing the silicon from the SiGe layer. Wide devices benefited from biaxial stress; narrow devices benefited even more from relaxation of perpendicular strain near the edges. In addition, back-gating can be used to modulate VT for greater design flexibility. The only downside was leakage that was still acceptable, but higher than pure silicon.
The result was the fastest ring oscillator yet reported: 11.2 ps/stage at 0.7 V.
Meanwhile, TSMC was dealing with the defects created by simply attempting to grow germanium on silicon epitaxially. Ordinarily, this creates threads of dislocations that migrate up through the entire grown layer, making it unsuitable for active use. But they found that if they grow the germanium after isolation and if the feature being grown is taller than it is wide (aspect ratio > ~1.4), then those threads stop propagating up when they hit the sidewall. This leaves a fin with a damaged bottom, but with a pristine upper portion that can be used as a channel. They refer to this as Aspect Ratio Trapping (ART). They claim it’s the first successful integration of pure germanium onto a FinFET platform, yielding excellent subthreshold characteristics, high performance, and good control of short-channel effects.
If you have the proceedings, the ETSOI paper is #18.1; the TSMC paper is #23.5.
posted by Bryon Moyer
Earlier this month, KLA-Tencor released their ICOS WI-2280 inspection tool for LEDs. Reading through all the things it does and the improvements in provides – things like enhanced recipe qualification and reduced setup time – well, for someone like me who doesn’t spend all his time in this world, you start to think… This sounds like a lot of other inspection tools. And there do seem to be a lot of different tools.
It makes you wonder, why can’t one tool simply do it all? Reading through what the 2280 does, it seems like it would be good stuff for any IC. So I asked that of them as one of those “OK, I feel really stupid asking this, but…” questions, and they clarified both why this is different from other IC inspection tools and what it is not intended to do.
First, and most fundamentally, LEDs use sapphire as a substrate, and it’s transparent. That means that different lighting is required as compared to a silicon wafer. I suppose you could argue that this should then just be a “setting” or adjustment on a more general-purpose tool. But that would fly up against a second concern: cost. The defects being detected on LEDs are in the 3-5-µm range, far larger than what you would look for on a 28-nm chip. No need to burden it with expensive micro-mote detection capabilities.
There’s also one other less obvious difference. LEDs are typically inspected again after dicing. It’s “relatively” easy to inspect dice on a wafer – once you align the wafer, you’re set. But with dice in trays, each die can shift around, so post-slicing inspection requires separate attention that’s not needed for standard ICs.
Meanwhile, the 2280 is intended for all in-line inspections of patterned wafers (or diced wafers). It’s not intended for sampling (which may use a slower, more detailed analysis) or for inspecting the blank substrate.
You can find out more in their release.