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Optimizing Power at the Architecture Level

by Bryon Moyer

May 30, 2012 at 2:52 PM

When Mentor handed their flagship HLS product, Catapult C, to Calypto almost a year ago, there were a lot of questions about the move. There could be technical, financial, personnel, all kinds of reasons.

Well, at least from a technical standpoint, Calypto just announced what they say was the driving factor: the natural synergy between Catapult C and the Calypto tools. In particular, their PowerPro tool, used for optimizing power.

Automated power optimization typically happens at a low level – typically using netlists (although analysis is moving up to the RTL level). But the real gains are to be had at the architectural level, which is far above RTL even. It’s the realm of untimed C/C++ and SystemC. It’s also the realm of HLS (high-level synthesis, more or less used synonymously with electronic system-level, or ESL). Which is where Catapult C plays.

So they’ve put the two together in a product they’re calling Catapult LP. While the standard Catapult SL can optimize area and performance, it can’t optimize power along with it. Catapult LP does all three by integrating PowerPro under the hood so that it can go figure out what the power will be for a given configuration.

Of course, in order for this to work, Catapult C has to generate RTL out of the high-level code, and then  that RTL has to be synthesized into gates for the low-level power work. Calypto actually has their own RTL synthesis engine which they say can match Synopsys DC results within 15%, which is close enough for architectural level estimation. Yes, they are tracking a tool that’s out of their control, but, realistically, Synopsys isn’t changing DC much these days, so it’s unlikely that there will be much work trying to keep up with the Synopsys updates.

So the designer can create one or more architectural configurations and then have the tool go figure out which one has the lowest power. While the RTL is synthesized in a feed-forward manner for area and performance based on constraints, the power element is managed in a feedback manner.  The gate-level representation can be optimized for clock gating etc. so that those effects can be included in the power estimate, but, at a high level, the designer generates the different options and then selects the one that’s lowest power (of the ones that meet the other constraints). The designer can influence the accuracy and run time through what Calypto calls an “elastic engine” that can be set to select either bit-level or word-level solvers, the former being more accurate but slower.

You can find more information in their release.

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