Back to Editors' Blog

High-Sigma Simulations

by Bryon Moyer

May 04, 2012 at 11:34 AM

We’ve noted before that the meaning of “corners” is much less obvious for analog circuits than it is for digital. Solido noted in a recent announcement that memory design in particular highlights the challenge. Memories are built of analog circuits that are repeated numerous times, and getting them all to yield on aggressive processes with enormous variation is a tough job.

They say that the standard Monte Carlo “run enough samples to cover the space, and then interpolate the gaps” approach has become untenable because of the number of samples that must be taken – billions – to capture a process with enough fidelity to capture problem areas. You can go with fewer points to simulate, but you may interpolate or extrapolate incorrectly – drastically so in some cases. In particular, if you’re trying for a high-sigma design, it’s unlikely that you’ll adequately check out the tails of the process.

So Solido has announced an enhanced form of meta-simulation: it’s a way they have of analyzing the sample set to determine which points to simulate rather than simulating them all. They claim they can run a 5-billion-sample set in as little 15 minutes. They claim no loss of confidence in the result as compared to running all 5 billion simulations.

You can find more information and a link to some whitepapers in their release

Channels

Analog/Mixed Signal. EDA. Semiconductor.

 
    submit to reddit  



Comments:

You must be logged in to leave a reply. Login »

Related Articles

FPGA-Prototyping Simplified

Cadence Rolls New Protium Platform

by Kevin Morris

System on Chip (SoC) design today is an incredibly complicated collaborative endeavor. By applying the label System to the chips we design, we enter a...

An Irregular Street Scene

Plasma-Therm Proposes Plasma Dicing

by Bryon Moyer

A silicon wafer will always be patterned with a perfect grid of rectangular dice. Its so obvious that you even have to think about...

Analog Breakthrough?

Pulsic Automates Analog Layout

by Bryon Moyer

You are now entering the It cant be done zone. But, at least for the moment, Ill ask that you relax that axiom,...

chipKITs and JPEGs

IP in Space and Open Source Board Buildin

by Amelia Dalton

It's time to break out the sparklers, an arc welder or two, and your best space suit - Fish Fry is here to celebrate! We're...

Crossbar RRAM Tweaks Nonvolatile Memory

Unique Resistive Technology Set to Challenge NAND Flash

by Jim Turley

I gotta say, memory chips are boring.

And thats coming from a guy who lives and works in the chip business. Sure, I...

Related Blog Posts

Improved FPGA Tool Results

by Bryon Moyer

Plunify tries to get the best out of FPGA design tools

TSVs: Like Vias, Only 1000X Deeper

by Bryon Moyer

Lining a 50-nm-deep via can be tough. So imagine changing nm to m to do a TSV

Synopsyss IP Initiative

by Bryon Moyer

Synopsys is taking a holistic view of SoC design using IP, including hardware and software elements.

KLA-Tencors New Reticle Inspector

by Bryon Moyer

The challenges of the latest semiconductor nodes place an extra burden on reticle inspection.

Mentor Unifies Verification

by Bryon Moyer

What used to be independent tools now serve a higher-level verification flow.


Login Required

In order to view this resource, you must log in to our site. Please sign in now.

If you don't already have an acount with us, registering is free and quick. Register now.

Sign In    Register