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Accelerating System Bandwidth with FPGAs and Hybrid Memory Cube

Move over DDR, the Hybrid Memory Cube (HMC) is here! But, from a design perspective, care and feeding of the amazing HMC can be a lot more demanding than DDR. In this episode of Chalk Talk, Amelia Dalton and Manish Deo of Altera explain how powerful FPGAs can help you tame the HMC in your next design.

SDAccel Development Environment Demonstration

This video demonstrates the SDAccel™ development environment for acceleration using a standard X86_64 workstation containing an Alpha data ADM-PCIE-7V3 accelerator.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

Assertion-Based Emulation Using Veloce

This paper describes the assertion-based verification approach along with its benefits and uses. It further explains the advantages of emulation, especially for very large and complex SoCs, and how Veloce® assertion synthesis improves the emulation of SoCs that include assertions and helps reduce the time to verification closure. The Veloce compiler synthesizes logic for the assertions along with the design under test (DUT) and maps them into the emulator, making emulation faster.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

Maximize Your Power and Efficiency with PADS Interactive Placement and Routing

For the engineer doing desktop PCB layout, efficiency is important. You don't want to waste precious time fighting with your PCB tool, and you don't want to end up with lousy results because you and your tool weren't getting along. Mentor Graphics PADS provides an efficient, high-productivity interactive placement and routing environment that lets you get great results quickly. In this episode of Chalk Talk, Amelia Dalton talks to Jim Martens of Mentor Graphics about interactive layout using PADS.

Verify Design Performance with PADS Best-in-Class Simulation and Analysis

It really isn't important to simulate your PCB design - as long as you don't care about re-spins, signal integrity, cost... OK, actually, there are many good reasons to simulate your board. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about simulating your board design using PADS. It may make you re-think your board design strategy.

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

FRAM Technology: The Next Generation of Non-volatile Memory for Microcontrollers

FRAM is one of the coolest non-volatile memory technologies to date. And, FRAM combined with microcontrollers is a perfect match. In this episode of Chalk Talk, Amelia Dalton chats with Will Cooper of Texas Instruments about the practical implications of FRAM technology in MCUs.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Xilinx at ARM TechCon 2014: Booth demonstration presented by National Instruments

Eric Myers, Product Manager for Embedded Products, National Instruments, demonstrates the Airbus Smart Tools concept for their Factory of the Future using the NI System on Module (SOM).

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

Function Enablement with 8-bit PIC Microcontrollers

For a lot of mainstream applications these days, 32-bit or even 16-bit processors are serious overkill. You can get great performance, smaller footprints, lower power consumption, and lower cost using 8-bit devices. In this episode of Chalk Talk, Amelia Dalton talks with Wayne Freeman of Microchip Technology about function enablement with 8-bit MCUs.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

Power-Aware Verification in Mixed-Signal Simulation

This paper presents the basic concepts of power-aware verification in mixed-signal simulation and applies them to the verification of a tire pressure monitoring system SoC, with the power architecture described in UPF. Many SoCs are mixed-signal in nature and have power-regulation functionality on the chip. Verifying such designs with mixed-signal simulation in power-aware mode complements digital verification by producing accurate results for the power management and analog units of a design.

New Approaches to Hardware Acceleration Using Ultra Low Density FPGAs

Ask system designers to list the problems they face – it doesn’t matter whether they’re building mobile consumer, automotive, industrial, medical or scientific applications – and inevitably they’ll mention optimizing host processor performance. It’s hardly surprising. The event-driven architecture of these MPUs allows them to multitask and address new priorities as they occur. But as the number of I/O continues to rise, it also places escalating demand on bandwidth. Tasked with managing a wider array of I/O as well as other system-wide command and control functions, today’s host MPUs must remain operational for longer periods of time, thereby consuming precious power and compute resources.

Industrial Temperature Measurement Solutions

Many industrial designs need data from sensors such as temperature probes. But, getting from the analog world of probe signals to the digital world where the magic happens can be a tedious and tricky process. In this episode of Chalk Talk, Amelia Dalton talks with Sean Long of Maxim Integrated about an easy way to connect up sensors such as temperature probes in your next industrial design.

OrCAD Now! Signal Integrity Presentation

Learn about the unique multi-tiered strategy to board analysis & verification designed to enable designers of all skill levels to analyze their PCB designs early in the development cycle when the cost of change is the lowest. This will also show how Cadence has created a multi-tier analysis environment that lets designers start with a set of pre-defined Electrical Rule Checks (ERC) that can be run on the board to quickly identify areas of interest or concern all without the need for any complex models or configurations.

Solving Today's Interface Challenges with Ultra-Low Density FPGA Bridging Solutions

Today’s embedded system designers face an unprecedented challenge from an I/O perspective. As system complexity rises, they are increasingly asked to address a multitude of potential I/O options. These options can range from interfacing one industry bus to another, to connecting new and higher performance sensors with mature application processors. Moreover, this problem is pervasive across all markets from high volume consumer applications to the latest industrial, scientific and medical systems.

Introducing SDAccel Development Environment

The SDAccel™ development environment for OpenCL™, C, and C++, enables up to 25X better performance/watt for data center application acceleration leveraging FPGAs. SDAccel, member of the SDx™ family, combines the industry’s first architecturally optimizing compiler supporting any combination of OpenCL, C, and C++ kernels, along with libraries, development boards and the first complete CPU/GPU like development and run-time experience for FPGAs.

chalk talks

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

It's the Software, Silly! - Success with FPGA-based Prototyping

Software is becoming a larger and larger part of our system-on-chip (SoC) designs. It is critical that we be able to begin developing and debugging software as early as possible in the design cycle. But, the hardware part of today's complex designs takes months to stabilize. In this episode of Chalk Talk, Amelia Dalton talks with Juergen Jaeger of Cadence about the tight relationship between software and emulation and how you can achieve success in your SoC design with a comprehensive emulation strategy.

Verification Methodologies (Made Easy)

Most FPGA designers don’t know much about formal methodologies for verification. It’s too bad, because today’s complicated FPGA designs can really take advantage of standardized methodologies like UVM. In this episode of Chalk TalkHD Amelia and Jerry Kaczynski (Aldec) are going to unscramble the anagrams and get you on your way to understanding and harnessing the power of universal verification methodologies - so you can start applying them to your next design.

Accelerated Design Productivity with the Kintex-7 FPGA Display Kit

In this episode of Chalk TalkHD Amelia gets into the guts of display technology with Aaron Behman of Xilinx. From the newest standards to the details of 4K2K, we will tell you how FPGAs are uniquely capable of meeting the extreme performance and power challenges posed by current and emerging video standards.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

It's an Analog World After All

It's an analog world out there. And, while most microcontrollers offer terrific features in the digital and software domain, Microchip has a new family of MCUs with Intelligent Analog capabilities that can make a huge difference in connecting your design to the real world. In this episode of Chalk Talk, Amelia Dalton talks to Alexis Alcott of Microchip about harnessing the power of Intelligent Analog in MCU design.

Smartphone and Tablet Accessory Design

In this episode of Chalk TalkHD Amelia Dalton talks to David Flowers from Microchip about creating tablet and smartphone accessories - and how it just may be easier than you think...

Rigid-Flex and Embedded Components

These days, flexibile circuit boards are making their way into the mainstream. Rigid-flex design gives us all kinds of new capabilities in form factor, as well as the opportunity to replace expensive and unreliable cables and connectors. But, how do you handle rigid-flex PCB design in your layout tools? In this episode of Chalk Talk, Amelia Dalton chats with Altium's Ben Jordan about rigid-flex design in Altium Designer - and how you can use those same capabilities for embedded components as a bonus!

latest papers and content

SDAccel Development Environment Demonstration

This video demonstrates the SDAccel™ development environment for acceleration using a standard X86_64 workstation containing an Alpha data ADM-PCIE-7V3 accelerator.

Introducing SDAccel Development Environment

The SDAccel™ development environment for OpenCL™, C, and C++, enables up to 25X better performance/watt for data center application acceleration leveraging FPGAs. SDAccel, member of the SDx™ family, combines the industry’s first architecturally optimizing compiler supporting any combination of OpenCL, C, and C++ kernels, along with libraries, development boards and the first complete CPU/GPU like development and run-time experience for FPGAs.

Power-Aware Verification in Mixed-Signal Simulation

This paper presents the basic concepts of power-aware verification in mixed-signal simulation and applies them to the verification of a tire pressure monitoring system SoC, with the power architecture described in UPF. Many SoCs are mixed-signal in nature and have power-regulation functionality on the chip. Verifying such designs with mixed-signal simulation in power-aware mode complements digital verification by producing accurate results for the power management and analog units of a design.

Assertion-Based Emulation Using Veloce

This paper describes the assertion-based verification approach along with its benefits and uses. It further explains the advantages of emulation, especially for very large and complex SoCs, and how Veloce® assertion synthesis improves the emulation of SoCs that include assertions and helps reduce the time to verification closure. The Veloce compiler synthesizes logic for the assertions along with the design under test (DUT) and maps them into the emulator, making emulation faster.

SoC Interconnect Verification

In this week's Whiteboard Wednesdays video, Tom Hackett discusses the VIP Catalog solution for SoC Interconnect Verification. Two products are provided: the Interconnect Validator, which monitors fabric behavior, and the Interconnect Workbench for performance analysis. The combined solution delivers functional verification along with latency and bandwidth analysis to fine-tune interconnect performance.

The Vault

Professional engineering projects require professional working practices. When we're designing things to be manufactured in volume, it's critical that we keep track of versions and revisions, collaborate and communicate effecitvely, and hand-off the right materials to manufacturing. In this episode of Chalk Talk, Amelia Dalton chats with Sam Sattel of Altium about Altium's "Vault" - which makes those professional practices a whole lot easier and smoother.

OrCAD Now! Signal Integrity Presentation

Learn about the unique multi-tiered strategy to board analysis & verification designed to enable designers of all skill levels to analyze their PCB designs early in the development cycle when the cost of change is the lowest. This will also show how Cadence has created a multi-tier analysis environment that lets designers start with a set of pre-defined Electrical Rule Checks (ERC) that can be run on the board to quickly identify areas of interest or concern all without the need for any complex models or configurations.

OrCAD Now – PSpice

This presentation is on the benefits of using PSpice® in an integrated OrCAD flow. For new users, it covers how to get started and where to find working examples. The next step is where to find specific models and how to create them if they’re not available anywhere. Finally it will go deeper into the tool to see how it can help us if we run into trouble by identifying parts that are close to failure.

Xilinx Product Teardown at ARM Tech Con: What's In There Besides Zynq SoCs?

Watch Steve Leibson, Editor of the Xilinx Xcell Daily Blog, moderate two product tear downs featuring the National Instruments Virtual Bench and the Cloudium Integrated Media Processing Platform.

Xilinx at ARM TechCon 2014: Booth demonstration presented by National Instruments

Eric Myers, Product Manager for Embedded Products, National Instruments, demonstrates the Airbus Smart Tools concept for their Factory of the Future using the NI System on Module (SOM).

TripleCheck VIP

In this week's Whiteboard Wednesdays video, Moshik Ruben discusses TripleCheck verification IP (VIP) and how it allows engineers to know they have a thoroughly tested design that complies with the interface specification.

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SmartFusion2 SoC FPGA Demo: Code Shadowing from SPI Flash to SDR Memory User’s Guide

This demo design shows SmartFusion®2 SoC FPGA device capabilities for code shadowing from serial peripheral interface (SPI) flash memory to single data rate (SDR) synchronous dynamic random access memory (SDRAM) and executing the code from SDR SDRAM. Code shadowing is a booting method that is used to execute an image from external faster volatile memories (DRAM) and is the process of copying the code from nonvolatile memory to volatile memory for execution. In performance critical applications, execution speed can be improved by code shadowing where code is copied to higher throughput RAM for faster execution.

Hardware Accelerated H.264 Video Encoding using VAAPI on the Intel® Atom™ Processor E6xx Series

The Intel® Atom™ Processor E6xx Series for the embedded devices market includes the POWERVR* VXE core that provides video encoding capabilities, allowing to encode high definition video streams in the highly compressed H.264 format with a very low main CPU utilization, releasing the general purpose processor for other parallel workloads. This processor feature is available to application developers by means of the open Video Acceleration API (VAAPI [1]). This paper explains how the VAAPI can be applied to a real time video encoding task, explaining the VAAPI function calls flow, and the corresponding parameters.

Optimize Your 28-nm FPGA Design for Maximum Performance

Want the best performance from your 28-nm FPGA design? Find out how you can make optimal use of Altera's 28-nm architecture to maximize your system performance. Watch this 10-minute webcast to learn about: Our 28-nm architecture innovations, Recommended design optimization techniques and Quartus® II software automated optimization tool.

Understanding the Impact of Single Event Effects in Networking Applications

Reliability of communication is essential in networking applications. The goal of five nines (99.999%) in network availability translates to less than six minutes in downtime in a year for the entire network. Among the many impacts on system reliability are the effects of ionizing radiation on electronic circuits. This radiation can cause memory elements in electronic circuits to change state. When this happens in the configuration memory of SRAM-based FPGAs, it can cause a change in the functionality of the circuit, greatly impacting system reliability. Designers of networking applications must understand the effect of this radiation and how to reduce the risk to the network.

Extending Silicon Convergence with Technology Innovations at 20nm

Altera’s technology innovations in 20nm devices will move customers’ designs up the silicon convergence continuum by providing them the ultimate system-integration platform to achieve unprecedented levels of performance, bandwidth, and power efficiency. These innovations will be delivered in a mixed-system fabric that brings together FPGA hardware and software flexibility along with the efficiencies of application-specific hard IP in a single device. Altera’s innovations in the mixed-system fabric are enabling customers to create differentiated system designs.

VeriSilicon and Cadence Customer Success Story

With the help of Cadence Software, VeriSilicon shortened their FPGA-based ASIC prototype development time by 75% and completed optimal pin assignment in one week vs. at least one month previously.

How to select specific rule checks for a Calibre DRC run

This video shows you how to create specific rule check recipes for running DRC in Calibre Interactive. Rule check recipes allow you to configure and reuse specific rule checks such as metal, density, and antenna checks across multiple Calibre DRC jobs. This will reduce the runtime for your Calibre DRC jobs and allows you to focus on the Calibre DRC results that you want to fix.

How to Design a Sigma Delta Mixer Circuit

In parts 1 & 2 of this 3-part Chalk Talk series, we talked about how Triad Semiconductor can save you 75%, or even as much as 99% in your next mixed-signal ASIC design. But, what good is savings if you don't know what you can design with it? In this third episode of our 3-part Chalk Talk series, Amelia and Reid Wender of Triad Semiconductor have fun taking ViaDesigner out for a spin - designing a sigma delta mixer.

CDNLive SV 2014: Avago Speeds Route and Timing Closure with Encounter Digital Implementation System

In this video from CDNLive Silicon Valley 2014, Jason Gentry, master IC design engineer for ASIC products division at Avago Technologies, describes how he used the Cadence® Encounter® digital implementation system's command line interface to add his own route-planner script and Encounter's multi-partition functionality to split the design into more levels of hierarchy. By doing so, Avago completed top-level route and timing closure in a lot less time—hours instead of days or weeks—because they were working on smaller pieces of the design in parallel. Learn more about the Encounter Digital Implementation System at http://bit.ly/1rlZpJ2.

Power Reduction in Next-Generation UltraScale Architecture

Designed to scale from 20 nm planar technology through 16 nm FinFET and beyond, Xilinx UltraScale™ devices equip an already-successful architectural platform with numerous innovative power reduction techniques. This white paper explores the challenges of managing power efficiently, reducing device power requirements, and innovating new power solutions at the speed of Moore's law.

Learn About Easier-to-Use Partial Reconfiguration Flow

Ever wonder whether the challenges of using partial reconfiguration are worth the benefits? Now, there's an easy-to-use, fine-grain partial reconfiguration methodology that delivers lower cost and power and higher system uptime. What's more, you don't need to understand the intricacies of FPGA architecture to get more usable density from your device.

MAX Series Configuration Controller Using Flash Memory

Altera’s flash memory configuration controller provides an alternative configuration solution for high-density FPGA-based designs. With the flexibility to use a bigger flash memory to store more configuration data, designers can implement the flash memory controller in MAX series devices for use in Stratix series, Arria series, and Cyclone series FPGAs. Configuration bitstream sizes are increasing with the higher-density FPGAs, which require larger devices to store and configure data.

Hardware in the Loop from the MATLAB/Simulink Environment

This white paper describes the tools, design flow, and verification of systems using Altera(r) FPGAs. It discusses the techniques of software simulation and hardware testing, and the challenges associated with them. This paper also describes the advantages of using the Hardware in the Loop (HIL) tool, which is part of Altera's software tools, to simplify software simulation and hardware testing in a variety of applications.

Actel FPGAs for Handheld Portable Applications

The portable electronics market is booming, and the continuing demand for smaller, more portable devices poses design challenges as end-users want more features, improved performance plus longer battery life. Actel’s nonvolatile flash FPGAs are unique in their ability to meet all the demands of the portable electronics designer: low active and static power consumption, small footprint packages, design security, higher integration, and live at power-up operation.

Optical Transport Networks for 100G Implementation in FPGAs

Due to their flexibility, FPGAs play a vital role for early adopters who want to design 100G systems today, prior to the standards being ratified. Altera Stratix IV GT FPGAs solve the problem for both 100G transport and 100G Ethernet by providing integrated 11.3-Gbps transceivers in the 40-nm technology node. In addition, Stratix IV GX, Arria II GX, and Arria II GZ FPGAs, and HardCopy series ASICs satisfy many application needs in OTNs and are cost-effective platforms for high-bandwidth systems

Why Do I Need a Customizable ARM-based SoC?

In this episode of Chalk TalkHD Amelia chats with Todd Koelling of Altera about what’s inside these new SoC FPGAs and how you can get started designing with them.

Transferring High-Speed Data over Long Distances with Combined FPGA and Multichannel Optical Modules

Today’s copper-based high-speed serial interfaces can deliver data at multi-gigabit rates. Data transfer rates exceeding 100 Gbps are possible by using multiple lanes in parallel, but are limited in the distance they can travel. One approach that improves the distance is to use optical interconnects rather than copper. Altera Corporation and Avago Technologies Inc. have jointly developed a solution that combines an FPGA and optical transmitter and receiver modules into a single integrated solution that can replace copper interconnects and multiple card-edge optical transceivers.

Wireless Transceiver Implementations

In this week's Whiteboard Wednesdays installment, Priyank Shukla highlights wireless transceivers and protocol standards 802.11x and LTE/LTE-A. Wireless transceiver implementation options consisting of RF, Analog Front-End (AFE), and Digital components are examined.


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