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SDAccel Development Environment Demonstration

This video demonstrates the SDAccel™ development environment for acceleration using a standard X86_64 workstation containing an Alpha data ADM-PCIE-7V3 accelerator.

Maximize Your Power and Efficiency with PADS Interactive Placement and Routing

For the engineer doing desktop PCB layout, efficiency is important. You don't want to waste precious time fighting with your PCB tool, and you don't want to end up with lousy results because you and your tool weren't getting along. Mentor Graphics PADS provides an efficient, high-productivity interactive placement and routing environment that lets you get great results quickly. In this episode of Chalk Talk, Amelia Dalton talks to Jim Martens of Mentor Graphics about interactive layout using PADS.

What is Electrically Aware Design?

For years, layout tools have focused on the pins and wires, the "froms" and "tos", the segments and nets - without considering that they were really creating a complex electrical circuit. Today, however, the electrical properties of our layout is critical, and issues like parasitic resistance and capacitance can have a dramatic effect on our final design. In this episode of Chalk Talk, Amelia Dalton chats with John Stabenow of Cadence about electrically-aware design with Cadence's Virtuoso.

Advanced System Management with Analog Non-volatile FPGAs

A system management device is critical to the successful power up, configuration, maintenance and power down of the system. As system complexity increases, the requirements of these devices are growing and features such as instant-on, analog capability, and flexibility are crucial. Read how a robust system management design incorporates a wide variety of tasks in both the analog and digital domain including power rail management, environmental condition management, and analytics for diagnostics and prognostics.

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

Synopsys ProtoCompiler for RTL Debug with HAPS Systems

Troy Scott, Product Marketing Manager, and Peter Zhang, R&D Engineer, explain RTL debug features available in ProtoCompiler.

Routing Interfaces Quickly & Efficiently on PCBs

In today's PCB designs, interfaces such as DDR pose major challenges for layout. Issues like timing and signal integrity can be tricky for even the most experienced designer. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about routing those tricky bits using a combination of automatic and manual routing techniques.

Solving Today's Interface Challenges with Ultra-Low Density FPGA Bridging Solutions

Today’s embedded system designers face an unprecedented challenge from an I/O perspective. As system complexity rises, they are increasingly asked to address a multitude of potential I/O options. These options can range from interfacing one industry bus to another, to connecting new and higher performance sensors with mature application processors. Moreover, this problem is pervasive across all markets from high volume consumer applications to the latest industrial, scientific and medical systems.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

Verify Design Performance with PADS Best-in-Class Simulation and Analysis

It really isn't important to simulate your PCB design - as long as you don't care about re-spins, signal integrity, cost... OK, actually, there are many good reasons to simulate your board. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about simulating your board design using PADS. It may make you re-think your board design strategy.

Rigid-Flex and Embedded Components

These days, flexibile circuit boards are making their way into the mainstream. Rigid-flex design gives us all kinds of new capabilities in form factor, as well as the opportunity to replace expensive and unreliable cables and connectors. But, how do you handle rigid-flex PCB design in your layout tools? In this episode of Chalk Talk, Amelia Dalton chats with Altium's Ben Jordan about rigid-flex design in Altium Designer - and how you can use those same capabilities for embedded components as a bonus!

Speed IP Bring-up and SoC Validation with HAPS-DX

Neil Songcuan, Sr. Product Marketing Manager, introduces the newest member of the HAPS family, HAPS Developer Express (HAPS-DX) and its features to speed IP bring-up and SoC validation

Accelerating Open Source Security Using OpenCL & Altera FPGAs

Today's FPGAs offer interesting potential for accelerating performance- and power-critical operations such as security algorithms. In this episode of Chalk Talk, Amelia Dalton chats with Ryan Kenny of Altera about using FPGAs to accelerate open source security algorithms written in OpenCL.

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

New Approaches to Hardware Acceleration Using Ultra Low Density FPGAs

Ask system designers to list the problems they face – it doesn’t matter whether they’re building mobile consumer, automotive, industrial, medical or scientific applications – and inevitably they’ll mention optimizing host processor performance. It’s hardly surprising. The event-driven architecture of these MPUs allows them to multitask and address new priorities as they occur. But as the number of I/O continues to rise, it also places escalating demand on bandwidth. Tasked with managing a wider array of I/O as well as other system-wide command and control functions, today’s host MPUs must remain operational for longer periods of time, thereby consuming precious power and compute resources.

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

OrCAD Now! Signal Integrity Presentation

Learn about the unique multi-tiered strategy to board analysis & verification designed to enable designers of all skill levels to analyze their PCB designs early in the development cycle when the cost of change is the lowest. This will also show how Cadence has created a multi-tier analysis environment that lets designers start with a set of pre-defined Electrical Rule Checks (ERC) that can be run on the board to quickly identify areas of interest or concern all without the need for any complex models or configurations.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

Function Enablement with 8-bit PIC Microcontrollers

For a lot of mainstream applications these days, 32-bit or even 16-bit processors are serious overkill. You can get great performance, smaller footprints, lower power consumption, and lower cost using 8-bit devices. In this episode of Chalk Talk, Amelia Dalton talks with Wayne Freeman of Microchip Technology about function enablement with 8-bit MCUs.

chalk talks

Maximize Your Power and Efficiency with PADS Interactive Placement and Routing

For the engineer doing desktop PCB layout, efficiency is important. You don't want to waste precious time fighting with your PCB tool, and you don't want to end up with lousy results because you and your tool weren't getting along. Mentor Graphics PADS provides an efficient, high-productivity interactive placement and routing environment that lets you get great results quickly. In this episode of Chalk Talk, Amelia Dalton talks to Jim Martens of Mentor Graphics about interactive layout using PADS.

Infineon's 8th Generation of RF Transistors Maximize Receiver Sensitivity and Range

If you're designing systems that use the latest WiFi standards, you know that a great RF transistor with high gain and low noise is key to good performance. In this episode of Chalk Talk, Amelia Dalton talks with Andrew Nelson of Infineon about the latest in high-performance RF transistors - Infineon's new 8th generation.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

DO-254 Requirements Traceability with Spec-TRACER

In this episode of Chalk TalkHD Amelia chats with Louie de Luna about Aldec's new Spec-TRACER tool and how Spec-TRACER helps you navigate your way through your design flow - from beginning to end, from requirements to verification.

Integrated Power and System Management

In this episode of Chalk TalkHD Amelia chats with Shyam Chandra of Lattice Semiconductor about an integrated approach to system and power management that will lighten your design load, improve your overall system design, and probably lower your total cost at the same time.

Battery Management Solutions

Designing battery-powered systems can be challenging. In addition to power and form-factor considerations, today's batteries require sophisticated charging and monitoring for maximum safety, life, and performance. In this episode of Chalk Talk, Amelia Dalton chats with Richard DelRossi of Texas Instruments about battery management solutions that can dramatically simplify your next battery-powered design while adding important monitoring capabilities to your device.

Accelerating System Bandwidth with FPGAs and Hybrid Memory Cube

Move over DDR, the Hybrid Memory Cube (HMC) is here! But, from a design perspective, care and feeding of the amazing HMC can be a lot more demanding than DDR. In this episode of Chalk Talk, Amelia Dalton and Manish Deo of Altera explain how powerful FPGAs can help you tame the HMC in your next design.

Getting Started Using Kintex-7 FPGAs for DSP

In this episode of Chalk TalkHD Amelia chats with Tom Hill of Xilinx about their new Kintex-7 DSP development kits that will finally get you onto the rocket-coaster of FPGA-powered DSP.

latest papers and content

SDAccel Development Environment Demonstration

This video demonstrates the SDAccel™ development environment for acceleration using a standard X86_64 workstation containing an Alpha data ADM-PCIE-7V3 accelerator.

Introducing SDAccel Development Environment

The SDAccel™ development environment for OpenCL™, C, and C++, enables up to 25X better performance/watt for data center application acceleration leveraging FPGAs. SDAccel, member of the SDx™ family, combines the industry’s first architecturally optimizing compiler supporting any combination of OpenCL, C, and C++ kernels, along with libraries, development boards and the first complete CPU/GPU like development and run-time experience for FPGAs.

Power-Aware Verification in Mixed-Signal Simulation

This paper presents the basic concepts of power-aware verification in mixed-signal simulation and applies them to the verification of a tire pressure monitoring system SoC, with the power architecture described in UPF. Many SoCs are mixed-signal in nature and have power-regulation functionality on the chip. Verifying such designs with mixed-signal simulation in power-aware mode complements digital verification by producing accurate results for the power management and analog units of a design.

Assertion-Based Emulation Using Veloce

This paper describes the assertion-based verification approach along with its benefits and uses. It further explains the advantages of emulation, especially for very large and complex SoCs, and how Veloce® assertion synthesis improves the emulation of SoCs that include assertions and helps reduce the time to verification closure. The Veloce compiler synthesizes logic for the assertions along with the design under test (DUT) and maps them into the emulator, making emulation faster.

SoC Interconnect Verification

In this week's Whiteboard Wednesdays video, Tom Hackett discusses the VIP Catalog solution for SoC Interconnect Verification. Two products are provided: the Interconnect Validator, which monitors fabric behavior, and the Interconnect Workbench for performance analysis. The combined solution delivers functional verification along with latency and bandwidth analysis to fine-tune interconnect performance.

The Vault

Professional engineering projects require professional working practices. When we're designing things to be manufactured in volume, it's critical that we keep track of versions and revisions, collaborate and communicate effecitvely, and hand-off the right materials to manufacturing. In this episode of Chalk Talk, Amelia Dalton chats with Sam Sattel of Altium about Altium's "Vault" - which makes those professional practices a whole lot easier and smoother.

OrCAD Now! Signal Integrity Presentation

Learn about the unique multi-tiered strategy to board analysis & verification designed to enable designers of all skill levels to analyze their PCB designs early in the development cycle when the cost of change is the lowest. This will also show how Cadence has created a multi-tier analysis environment that lets designers start with a set of pre-defined Electrical Rule Checks (ERC) that can be run on the board to quickly identify areas of interest or concern all without the need for any complex models or configurations.

OrCAD Now – PSpice

This presentation is on the benefits of using PSpice® in an integrated OrCAD flow. For new users, it covers how to get started and where to find working examples. The next step is where to find specific models and how to create them if they’re not available anywhere. Finally it will go deeper into the tool to see how it can help us if we run into trouble by identifying parts that are close to failure.

Xilinx Product Teardown at ARM Tech Con: What's In There Besides Zynq SoCs?

Watch Steve Leibson, Editor of the Xilinx Xcell Daily Blog, moderate two product tear downs featuring the National Instruments Virtual Bench and the Cloudium Integrated Media Processing Platform.

Xilinx at ARM TechCon 2014: Booth demonstration presented by National Instruments

Eric Myers, Product Manager for Embedded Products, National Instruments, demonstrates the Airbus Smart Tools concept for their Factory of the Future using the NI System on Module (SOM).

TripleCheck VIP

In this week's Whiteboard Wednesdays video, Moshik Ruben discusses TripleCheck verification IP (VIP) and how it allows engineers to know they have a thoroughly tested design that complies with the interface specification.

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IGLOO FPGA Product Brief

IGLOO®2 FPGAs integrate fourth generation flash-based FPGA fabric and high performance communications interfaces on a single chip. The IGLOO2 family is the industry’s lowest power, most reliable and highest security programmable logic solution. This next generation IGLOO2 architecture offers up to 3.6X gate count implemented with 4-input look-up table (LUT) fabric with carry chains, giving 2X performance, and includes multiple embedded memory options and math blocks for digital signal processing (DSP)and much, much more.

SoC Interconnect Verification

In this week's Whiteboard Wednesdays video, Tom Hackett discusses the VIP Catalog solution for SoC Interconnect Verification. Two products are provided: the Interconnect Validator, which monitors fabric behavior, and the Interconnect Workbench for performance analysis. The combined solution delivers functional verification along with latency and bandwidth analysis to fine-tune interconnect performance.

Allegro 16.5 Powers up Allegro PCB PDN Analysis

This is a Cadence blog post about the launch of the Allegro PDN Analysis and what it will mean for PCB designers.

Automotive Top Ten - Ten Points to Consider When Using Logic in Your Next Automotive Design

Automotive electronics designers have been turning more frequently to programmable logic solutions to meet the needs of their next generation designs. FPGAs offer time-to-market benefits along with simplified qualification and greater flexibility in comparison to historic ASIC-based solutions. Actel is a leading supplier of FPGAs to the automotive industry. Actel parts are being used in the most demanding mission-critical systems, such as powertrain and safety subsystems, in addition to infotainment and body electronics designs.

Six Ways to Replace a Microcontroller With a CPLD

With the advent of low-power CPLDs, low-power electronic product designers now have new options for implementing many of the functions traditionally performed by microcontrollers. This white paper discusses when it is advantageous to use a CPLD instead of a microcontroller, and when it makes sense to use a CPLD as a companion to a microcontroller, with examples grouped into three categories—I/O management, port management, and system management—based on their function and level of complexity.

Single-Event Effect Mitigation in RTAX-DSP Space-Flight FPGAs

When high-energy ions present in space strike the substrate of an IC, their impact can cause momentary current/voltage pulses in the IC’s circuitry. When these pulses are sufficient to change the data on the circuit, they are referred to collectively as single-event effects (SEEs).

The Industry's First 20nm and UltraScale FPGAs and 3D ICs

The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system level performance for the most demanding applications.

Understanding the Impact of Single Event Effects in Networking Applications

Reliability of communication is essential in networking applications. The goal of five nines (99.999%) in network availability translates to less than six minutes in downtime in a year for the entire network. Among the many impacts on system reliability are the effects of ionizing radiation on electronic circuits. This radiation can cause memory elements in electronic circuits to change state. When this happens in the configuration memory of SRAM-based FPGAs, it can cause a change in the functionality of the circuit, greatly impacting system reliability. Designers of networking applications must understand the effect of this radiation and how to reduce the risk to the network.

ASIC Prototyping Simplified

To use current solutions for application-specific integrated circuit (ASIC) prototyping using field-programmable gate arrays (FPGAs), you either have to create custom boards or buy off-the-shelf FPGA boards. Off-the-shelf boards don’t satisfy the requirements for complex systems on chips (SOCs), and they’re expensive and lack scalability. Cadence Allegro FPGA System Planner fills the gap, offering a simplified approach to ASIC prototyping.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Designing a Power Distribution Network for High-End FPGAs

Progress to smaller FPGA process geometries has led to shrinking noise margins and lower voltages. These changes mandate higher currents, tighter voltage tolerances, and management of multiple power rails. Every board designer has to learn how to deliver clean power to the FPGA, as making the wrong choice can severely reduce functionality and performance.

Put 1080p High-Definition Analytics into Your IP Camera

Advanced analytics is replacing simple motion detection in surveillance cameras. See how you can get 1080p high-definition (HD) analytics in your IP camera with a single-chip video analytics solution.

SmartFusion Intelligent Mixed Signal FPGAs in Motor Control Applications

This video provides an exploration of Motor Control applications using Actel's SmartFusion™ intelligent mixed signal flash FPGAs for field-oriented closed-loop motor control for brushless DC (PMSM) motors, with a closer look at your challenges and a look into the Actel motor control development kit currently in development.

Extending the Spartan-6 FPGA Connectivity TRD (PCIe-DMA-DDR3-GbE) to Support the Aurora 8B/10B Serial Protocol

Targeted Reference Designs (TRDs) provide Xilinx designers with turn-key platforms to create FPGA based solutions in a wide variety of industries. This application note extends the Spartan-6 FPGA PCIe-DMA-DDR3-GbE TRD to support Aurora 8B/10B serial protocol.

Using 10-Gbps Transceivers in 40G/100G Applications (REVISED)

This white paper identifies the drivers behind the migration to 100G interfaces, and shows how to leverage FPGAs to implement this high-speed interface. The emerging 40GbE and 100GbE standards for data center and core network systems rely heavily on FPGAs to share those sectors with other protocol infrastructures. In addition to providing an unprecedented amount of resources such as logic, on-chip memory, and DSP blocks, Altera Stratix IV devices are the only FPGA family to enable these designs.

Effective Version Control for Electronic Design

When it comes to our hardware engineering projects, we need to keep our design data well organized. In the software world, this is accomplished with the help of version control systems. Unfortunately, most of us don’t learn version control for hardware design. In this episode of Chalk TalkHD Amelia chats with Ben Jordan of Altium about how effective version control can help every step of the design process, enable team design, manage versions and configurations, and keep our project from spiraling out of control.

Multiplying the Value of 20nm with UltraScale Devices: Doing More for Less

Xilinx is multiplying the value of 20nm with the UltraScale™ architecture and associated family of FPGAs and 3D ICs. Whether viewed from almost every attribute at the chip level or viewed when integrating multiple chips into one or fewer chips at the system level, you will find compelling value metrics as you migrate to an UltraScale solution. UltraScale architecture and Vivado® Design Suite are co-optimized to enable a device utilization target of 90%, which can result in up to a 30% effective cost advantage for the next generation of smarter, high performance systems in: Packet processing: Multi-hundred gigabit throughput Waveform processing: Multi-teraMAC throughput Image and video processing: 8K4K image and video processing and transport High performance computing: Multi-teraflop throughput Learn More about potential chip and system level value multipliers.

Achieving 25 Gbps Transceiver Performance on 28nm FPGAs

Need high bandwidth for your next-generation design? Watch our 9-minute video to see 25-Gbps transceiver performance on a 28nm device. You will: See a live demo of our 28nm transceiver technology running a pseudo-random bit pattern at 25 Gbps, See transmit and receive eye diagrams across a 10GBASE-KR backplane running at 10 Gbps, Learn more about our 28nm Stratix® V FPGAs, which feature integrated 28-Gbps transceivers.


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