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Recommended Reading

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.

The UltraScale Architecture for Highest Utilization and Superior Performance

The UltraScale™ architecture introduces many innovations over traditional FPGA architectures that increase performance and reduce power consumption. In this video, we will focus on enhancements to the routing, logic and implementation software that result in an architecture allowing for the device to be highly utilized while still maintaining performance, and keeping runtime low.

Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform

Increasing design complexities and the rapidly increasing number of scenarios impede the timing closure process. ECO techniques that have good single-pass fix rates can reduce the number of iterations through the extraction, implementation, and final signoff loop for fastest timing closure.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

Delivering Higher FPGA Utilization & Performance: UltraScale Architecture

Ever notice how hard it can be to get the full utilization that an FPGA datasheet promises? Xilinx is aiming to change all that. In this episode of Chalk Talk, Amelia Dalton talks with Darren Zacher of Xilinx about the new Ultrascale FPGA family, and how the architecture has been optimized for maximum utilization.

Protium Rapid Prototyping Platform

Building a robust prototype involves a lot more than just throwing a bunch of big FPGAs on a board or in a box. In fact, success of a prototype is a lot more about the system surrounding the boards - the tools, design flow, and IP that make the whole thing come up easily and work smoothly. In this episode of Chalk Talk, Amelia Dalton talks to Juergen Jaeger of Cadence about the new Protium Rapid Prototyping Platform from Cadence, and how it can simplify your prototyping process.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

Accelerating System Bandwidth with FPGAs and Hybrid Memory Cube

Move over DDR, the Hybrid Memory Cube (HMC) is here! But, from a design perspective, care and feeding of the amazing HMC can be a lot more demanding than DDR. In this episode of Chalk Talk, Amelia Dalton and Manish Deo of Altera explain how powerful FPGAs can help you tame the HMC in your next design.

Advanced System Management with Analog Non-volatile FPGAs

A system management device is critical to the successful power up, configuration, maintenance and power down of the system. As system complexity increases, the requirements of these devices are growing and features such as instant-on, analog capability, and flexibility are crucial. Read how a robust system management design incorporates a wide variety of tasks in both the analog and digital domain including power rail management, environmental condition management, and analytics for diagnostics and prognostics.

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

It's an Analog World After All

It's an analog world out there. And, while most microcontrollers offer terrific features in the digital and software domain, Microchip has a new family of MCUs with Intelligent Analog capabilities that can make a huge difference in connecting your design to the real world. In this episode of Chalk Talk, Amelia Dalton talks to Alexis Alcott of Microchip about harnessing the power of Intelligent Analog in MCU design.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

OrCAD Constraint Driven Design Flow

The OrCAD constraint driven flow provides a unique, fully integrated environment to define design intent and dynamically track compliance throughout the entire implementation process. This slideshow is demonstrating how to utilize the constraint driven flow in OrCAD to improve efficiency, reduce errors, and help ensure on-time product delivery.

UltraScale Architecture: Highest Device Utilization, Performance, and Scalability

The UltraScale™ architecture provides numerous technical innovations to exceed the utilization and performance demands of next-generation applications, all while offering both architectural migration and package footprint migration for optimal design reuse.

Architecture Matters: Three Architectural Insights for SoC FPGAs

New devices that combine the power and flexiblility of FPGAs and conventional processors on a single chip represent a breakthrough in capability. But, understanding the complex architecture of these sophisticated components requires us to look under the hood to see how the architecture fits our design requirements, and how to choose the right chip for our application. In this episode of Chalk Talk, Amelia Dalton talks with Todd Koelling of Altera about what to look for in the architecture of your SoC FPGA.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Static Timing Analysis and Constraint Validation

Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Design Data Management with PTC Windchill and Cadence Allegro PCB

Learn how PTC and Cadence have developed a unique collaboration environment to connect Allegro PCB design data with the Windchill PLM system for robust file management and check-in check-out capabilities.

chalk talks

Infineon's 8th Generation of RF Transistors Maximize Receiver Sensitivity and Range

If you're designing systems that use the latest WiFi standards, you know that a great RF transistor with high gain and low noise is key to good performance. In this episode of Chalk Talk, Amelia Dalton talks with Andrew Nelson of Infineon about the latest in high-performance RF transistors - Infineon's new 8th generation.

Solving the 100Gbps Challenge with ABAX2

What do you do when plain-old FPGAs leave too much on the table to handle your next bandwidth challenge efficiently? In this episode of Chalk TalkHD Amelia chats with Christian Plante (Tabula) about Tabula's new ABAX2 devices - based on their innovative Spacetime architecture. ABAX2 is fabricated on the latest Intel 22nm Tri-Gate technology, and can give you an enormous advantage in your next 100G design.

Verification Methodologies (Made Easy)

Most FPGA designers don’t know much about formal methodologies for verification. It’s too bad, because today’s complicated FPGA designs can really take advantage of standardized methodologies like UVM. In this episode of Chalk TalkHD Amelia and Jerry Kaczynski (Aldec) are going to unscramble the anagrams and get you on your way to understanding and harnessing the power of universal verification methodologies - so you can start applying them to your next design.

Accelerating Open Source Security Using OpenCL & Altera FPGAs

Today's FPGAs offer interesting potential for accelerating performance- and power-critical operations such as security algorithms. In this episode of Chalk Talk, Amelia Dalton chats with Ryan Kenny of Altera about using FPGAs to accelerate open source security algorithms written in OpenCL.

The Hardware Prototype Arrives -- Find Design Errors Fast and Improve Design Quality

In this episode of Chalk TalkHD Amelia chats with Bob Potock (Kozio) about how you can save yourself a bunch of headaches at prototype time and how Kozio’s VTOS (Verification and Test Operating System) can solve all of your embedded design prototyping problems.

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

It's an Analog World After All

It's an analog world out there. And, while most microcontrollers offer terrific features in the digital and software domain, Microchip has a new family of MCUs with Intelligent Analog capabilities that can make a huge difference in connecting your design to the real world. In this episode of Chalk Talk, Amelia Dalton talks to Alexis Alcott of Microchip about harnessing the power of Intelligent Analog in MCU design.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

latest papers and content

Three Ways that Allegro TimingVision Environment Speeds Up Timing Closure of High-Speed PCB Interfaces

On advanced high-speed interfaces, timing closure can be an iterative process that can be time-consuming and frustrating. PCB designers need techniques and tools to make the process more efficient, so they can contribute to an overall faster time to market for the design. This article discusses three ways that the new Cadence Allegro TimingVision Environment speeds up timing closure of high-speed PCB interfaces.

Architecture Matters: Three Architectural Insights for SoC FPGAs

New devices that combine the power and flexiblility of FPGAs and conventional processors on a single chip represent a breakthrough in capability. But, understanding the complex architecture of these sophisticated components requires us to look under the hood to see how the architecture fits our design requirements, and how to choose the right chip for our application. In this episode of Chalk Talk, Amelia Dalton talks with Todd Koelling of Altera about what to look for in the architecture of your SoC FPGA.

Addressing the Advantages of Embedded LTE and Advanced LTE

In this week's Whiteboard Wednesdays video, Bob Salem discusses the advantages of embedding a LTE and Advanced LTE analog block on the SoC to support many of the mobile applications in the market today.

Delivering Higher FPGA Utilization & Performance: UltraScale Architecture

Ever notice how hard it can be to get the full utilization that an FPGA datasheet promises? Xilinx is aiming to change all that. In this episode of Chalk Talk, Amelia Dalton talks with Darren Zacher of Xilinx about the new Ultrascale FPGA family, and how the architecture has been optimized for maximum utilization.

A Faster, More Accurate Approach for System-Level Performance Verification of a Wireless RFIC Design

Wireless RFIC designers are expected to be experts on a variety of ever-changing wireless standards and protocols. They must also contend with time-consuming manual simulation setup and post-processing of the simulation results. This paper discusses how an advanced simulation methodology, involving characterization and modeling of a RFIC design, enhances both the speed and the accuracy of system-level performance verification of a wireless RFIC.

UltraScale Architecture: Highest Device Utilization, Performance, and Scalability

The UltraScale™ architecture provides numerous technical innovations to exceed the utilization and performance demands of next-generation applications, all while offering both architectural migration and package footprint migration for optimal design reuse.

The UltraScale Architecture for Highest Utilization and Superior Performance

The UltraScale™ architecture introduces many innovations over traditional FPGA architectures that increase performance and reduce power consumption. In this video, we will focus on enhancements to the routing, logic and implementation software that result in an architecture allowing for the device to be highly utilized while still maintaining performance, and keeping runtime low.

OrCAD Constraint Driven Design Flow

The OrCAD constraint driven flow provides a unique, fully integrated environment to define design intent and dynamically track compliance throughout the entire implementation process. This slideshow is demonstrating how to utilize the constraint driven flow in OrCAD to improve efficiency, reduce errors, and help ensure on-time product delivery.

Design Data Management with PTC Windchill and Cadence Allegro PCB

Learn how PTC and Cadence have developed a unique collaboration environment to connect Allegro PCB design data with the Windchill PLM system for robust file management and check-in check-out capabilities.

Consumer DRAM Trends

In this week's Whiteboard Wednesdays video, Lou Ternullo explains the DRAM trends in today's consumer market. He deep dives into the comparison between LPDDR4 and DDR4 DRAM.

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Power Estimation and Management for MachXO2 Devices

A key requirement for many of today’s high volume FPGA applications is low power consumption. The MachXO2™ PLD provides many power-saving features including Power Controller, Bank Controller and Power Guard. This technical note provides users with detail for using the MachXO2 low power architectural features including power supply considerations and power estimations provided by the Power Calculator tool.

Implementing FIR Filters and FFTs with 28nm Variable-Precision DSP Architecture

Across applications, the two most common functions implemented in FPGA-based high-performance signal processing are FIR filters and FFTs. The FPGA’s DSP architecture must be optimized to allow the most efficient implementation of these structures as this directly translates into cost and power benefits to the customer. This paper introduces the DSP architecture of the latest 28nm Altera® FPGAs and shows how this architecture enables the most efficient implementation of FIR filters and FFTs.

Generating Functionally Equivalent FPGAs and ASICs With a Single Set of RTL and Synthesis/Timing Constraints

Electronic systems designers use FPGAs for their prototype implementations, taking advantage of the devices’ reprogrammability to validate hardware and software. Once the design is ready for volume production, certain types of ASICs help the designers meet power, performance, and cost targets. This paper discusses the evolution, architecture, and capabilities of Altera HardCopy ASICs as a package- and pin-compatible FPGA counterpart that is ideal for taking designs into volume production.

OpenCL on FPGAs: Accelerating Performance and Design Productivity

FPGAs have amazing capabilities when it comes to accelerating performance-critical algorithms at a tiny fraction of the power it would require to run them in software. The marriage of FPGAs with conventional CPUs could provide a truly remarkable high-performance computing platform. However, the problem has always been how to program it. In this episode of Chalk TalkHD Amelia chats with Albert Chang of Altera about about how OpenCL can now be used to program FPGAs. OpenCL is already very popular for programming systems with graphics processors (GPUs). Now, Altera has enabled us to use this same language to program FPGA+CPU systems.

Improving Hardware Verification with Accelerated Verification IP (VIP)

In this week's Whiteboard Wednesdays video, Tom Hackett talks about Accelerated Verification IP (VIP) and how it makes hardware verification more efficient and productive.

Increased Productivity Using Team Design

Xilinx® FPGAs offer up to 2 million logic cells in capacity—and they continue to grow. Designs of this complexity usually require a team of developers, and often, a team leader, who is responsible for the synthesis and implementation of the entire design. To make matters more challenging, the developers can be located internationally, with different portions of the design developed in different locations, and even by different companies. The Xilinx Team Design flow introduced in ISE® Design Suite 13.1 focuses on solving these challenges.

Reducing Total System Cost with Low-Power 28nm FPGAs

Altera® Cyclone® V FPGAs help designers reduce total system cost in a number of ways. Designers benefit not only from TSMC’s 28-nm Low Power (28LP) manufacturing process, but also from the architectural decisions that have gone into the Cyclone V device family and the array of powerful productivity-enhancing tools featured in Altera’s design tool ecosystem. With Cyclone V FPGAs, customers not only enjoy the lowest cost of ownership in the industry, but the widest array of low-cost parts available—from 25K logic elements (LE) to 301K LEs—and the only 28-nm solution under 100K LEs.

Mastering the Magic of Multi-Patterning

Multi-patterning technology was introduced at the 20 nm node to overcome lithographic limitations in current IC manufacturing processes. Successfully implementing multi-patterning compliance in the IC design and verification flow requires a thorough understanding of multi-patterning techniques and their impact on your design. Learn what multi-patterning is, why you need it, and how Calibre® Multi-Patterning software can help you effectively and efficiently incorporate multi-patterning into your leading-edge designs.

PCIe Controller Solution

In this week's Whiteboard Wednesdays video, Sandeep Brahmadathan breaks down Cadence's high-performance, low-latency controller solution for PCI Express (PCIe).

OTN Transport of Baseband Radio Serial Protocols in C-RAN Architecture for Mobile Network Applications

This joint white paper by MTI Mobile and Altera presents a proof of concept implementation of digital baseband radio data transport over Optical Transport Network (OTN) compliant to 3GPP Long Term Evolution – Advanced (LTE-A) standard, which enables us to exploit the benefits of Cloud Radio Access Network (C-RAN) architecture. The purpose of this paper is to demonstrate that data transport between the MTI Radiocomp’s baseband module and a remote radio module over an OTN-compliant mapper from Altera is compliant to Common Public Radio Interface (CPRI) and to the OBSAI interface protocols.

Optimize Power and Cost with Altera’s Diversified 28nm Device Portfolio (REVISED)

Altera’s 28-nm devices provide a diversified product portfolio tailored to support a broad spectrum of applications, ranging from low cost and power, to high-end applications. This white paper describes the power and cost advantages of Altera’s Stratix® V, Cyclone® V, Arria® V, and HardCopy® V devices.

Lowering Power at 28nm with Xilinx 7 Series FPGAs

This white paper describes several aspects of power related to the Xilinx® 28nm 7 series FPGAs, including the TSMC 28nm high-k metal gate (HKMG), high performance, low power (28nm HPLor 28 HPL) process choice. The power benefits afforded by the 28 HPL process and its usefulness across Xilinx's full product offerings is described as well as the architectural innovations and features for power reduction across the dimensions of static power, dynamic power, and I/O power.

Verification IP Productivity Tools

In this week's Whiteboard Wednesdays video, Tom Hackett talks about Cadence Verification IP (VIP) productivity tools in the VIP catalog. These tools, PureView and TripleCheck, help engineers better match their VIP to their design under test ensuring better verified designs.

SmartFusion Intelligent Mixed Signal FPGAs in Motor Control Applications

This video provides an exploration of Motor Control applications using Actel's SmartFusion™ intelligent mixed signal flash FPGAs for field-oriented closed-loop motor control for brushless DC (PMSM) motors, with a closer look at your challenges and a look into the Actel motor control development kit currently in development.

ASIC Prototyping Simplified

To use current solutions for application-specific integrated circuit (ASIC) prototyping using field-programmable gate arrays (FPGAs), you either have to create custom boards or buy off-the-shelf FPGA boards. Off-the-shelf boards don’t satisfy the requirements for complex systems on chips (SOCs), and they’re expensive and lack scalability. Cadence Allegro FPGA System Planner fills the gap, offering a simplified approach to ASIC prototyping.

Advanced Layout & Routing Techniques

Get an update from PCB Layout as this presentation walks through the latest techniques to help tackle your tough PCB design challenges. It will cover constraint management, advanced multi-signal routing, DDR implementation, automated placement & reuse, and more. View if you want learn how you can save time and reduce errors during PCB layout.

Super Low Power MCUs: NanoWatt XLP Technology

In this episode of Chalk TalkHD Amelia chats with Jason Tollefson of Microchip Technology about a radical new line of microcontrollers from Microchip that combine amazing processing capability with almost unbelievably low power consumption.

Introducing Xilinx Ultrascale™ Architecture: Industry’s First ASIC-Class All Programmable Architecture

The UltraScale™ Architecture addresses these challenges by applying leading-edge ASIC techniques in a fully programmable architecture. This architecture scales from 20nm planar through 16nm FinFET technologies and beyond, while also scaling from monolithic through 3D ICs. The UltraScale architecture not only addresses the limitations to scalability of total system throughput and latency, but directly addresses interconnect - the number one bottleneck to system performance at advanced nodes.


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