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Cadence Allegro PCB Design Solution

Allegro PCB Designer is a scalable, proven PCB design environment that addresses technological and methodological challenges while making the design cycles shorter and predictable. Read how Allegro PCB Design Solution can manage complexity for faster, more cost-effective implementations.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

Mastering the Magic of Multi-Patterning

Multi-patterning technology was introduced at the 20 nm node to overcome lithographic limitations in current IC manufacturing processes. Successfully implementing multi-patterning compliance in the IC design and verification flow requires a thorough understanding of multi-patterning techniques and their impact on your design. Learn what multi-patterning is, why you need it, and how Calibre® Multi-Patterning software can help you effectively and efficiently incorporate multi-patterning into your leading-edge designs.

Static Timing Analysis and Constraint Validation

Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.

Selecting the Right PHY Solution

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty reviews evaluation criteria when purchasing a PHY IP solution. Kishore details topics such as power, performance, and area (PPA), interoperability, DFI, and floorplan flexibilty.

Ethernet in Cars

In this week's Whiteboard Wednesdays video, Arthur Marris introduces the next big thing in the Ethernet space—Ethernet in cars. With its high data rate, lightweight cabling, and distributed networking capabilities, as well as the fact that it is an interoperable open standard and works well with TCP/IP, Ethernet is ideal for addressing many of the challenges facing automotive engineers.

Rigid-Flex and Embedded Components

These days, flexibile circuit boards are making their way into the mainstream. Rigid-flex design gives us all kinds of new capabilities in form factor, as well as the opportunity to replace expensive and unreliable cables and connectors. But, how do you handle rigid-flex PCB design in your layout tools? In this episode of Chalk Talk, Amelia Dalton chats with Altium's Ben Jordan about rigid-flex design in Altium Designer - and how you can use those same capabilities for embedded components as a bonus!

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

It's an Analog World After All

It's an analog world out there. And, while most microcontrollers offer terrific features in the digital and software domain, Microchip has a new family of MCUs with Intelligent Analog capabilities that can make a huge difference in connecting your design to the real world. In this episode of Chalk Talk, Amelia Dalton talks to Alexis Alcott of Microchip about harnessing the power of Intelligent Analog in MCU design.

Industrial Temperature Measurement Solutions

Many industrial designs need data from sensors such as temperature probes. But, getting from the analog world of probe signals to the digital world where the magic happens can be a tedious and tricky process. In this episode of Chalk Talk, Amelia Dalton talks with Sean Long of Maxim Integrated about an easy way to connect up sensors such as temperature probes in your next industrial design.

Protium Rapid Prototyping Platform

Building a robust prototype involves a lot more than just throwing a bunch of big FPGAs on a board or in a box. In fact, success of a prototype is a lot more about the system surrounding the boards - the tools, design flow, and IP that make the whole thing come up easily and work smoothly. In this episode of Chalk Talk, Amelia Dalton talks to Juergen Jaeger of Cadence about the new Protium Rapid Prototyping Platform from Cadence, and how it can simplify your prototyping process.

Five Ways to Build Flexibility into Industrial Applications with FPGAs

System complexity continues to increase in industrial designs such as communications, motor control, I/O modules and image processing. Read how FPGAs offer the ability to integrate an entire SoC at a lower cost compared to discrete MCU, DSP, ASSP, or ASIC solutions. Whether used as a coprocessor or SoC, FPGAs offer the following advantages for your industrial applications: · Design integration to simplify and reduce cost · Reprogrammability to adapt industrial designs to evolving protocols · Performance scaling to meet your system requirements. · Obsolescence protection through long FPGA life cycles and device migration

Accelerating Open Source Security Using OpenCL & Altera FPGAs

Today's FPGAs offer interesting potential for accelerating performance- and power-critical operations such as security algorithms. In this episode of Chalk Talk, Amelia Dalton chats with Ryan Kenny of Altera about using FPGAs to accelerate open source security algorithms written in OpenCL.

Methods and Tools for Bring-Up and Debug of an FPGA-Based ASIC Prototype

Software simulation of RTL is no longer capable of providing all of the verification required for today's complex ASIC designs. Modern ASICs are a complex mixture of hardware and software, so it is necessary to verify the design within the context of the complete system, running the full range of software at speeds that approach real-time. Successfully validating an ASIC design on an FPGA-based prototype before committing to silicon is now a key project milestone for most design teams. This paper examines some of the best practices for both successful bring-up and logic debug of ASICs using FPGA-based prototypes.

Cadence and IBM: Customer Success Story

“The Cadence solution enables us to enter up to 99 percent of signals in table format, which, along with improved analytics and a unique integrated environment, reduced our PCB development time by 80 percent.” Learn why Gisbert Thomke, a group leader at IBM is able to say that and how exactly the company accelerates large-scale PCB system design using unique cadence multi-style design entry solution.

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

Intelligently Expanding Microprocessor Connectivity Using Low-cost FPGAs

Whether they be CPUs, microprocessors or microcontrollers, microprocessors are an indispensable component in modern electronic system design. However, as systems become more complex and host a wider array of features and user interfaces, system architects using mid-range microprocessors in particular typically face three key challenges connecting the microprocessor, or microprocessors, they are using to the rest of their system: implementing more than 150 general purpose I/Os (GPIO), finding cost effective solutions in the 100 to 150 GPIO range, and matching available I/O peripherals with system needs.

Infineon's 8th Generation of RF Transistors Maximize Receiver Sensitivity and Range

If you're designing systems that use the latest WiFi standards, you know that a great RF transistor with high gain and low noise is key to good performance. In this episode of Chalk Talk, Amelia Dalton talks with Andrew Nelson of Infineon about the latest in high-performance RF transistors - Infineon's new 8th generation.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

chalk talks

Solving the 100Gbps Challenge with ABAX2

What do you do when plain-old FPGAs leave too much on the table to handle your next bandwidth challenge efficiently? In this episode of Chalk TalkHD Amelia chats with Christian Plante (Tabula) about Tabula's new ABAX2 devices - based on their innovative Spacetime architecture. ABAX2 is fabricated on the latest Intel 22nm Tri-Gate technology, and can give you an enormous advantage in your next 100G design.

IP and Process Solutions for Energy-efficient PMICs

In this episode of Chalk TalkHD Amelia chats with Ravi Mahatme from ARM and King Ou from GLOBALFOUNDRIES about how IP and process solutions can help solve our power management problems.

High Speed Data Acquisition and Software Defined Radio Made Simple

Building a hybrid computing platform from scratch is a huge and complicated project. Luckily, somebody has already done that work for you. In this episode of Chalk TalkHD Amelia chats with Justin Braun (4DSP) about how you can use pre-designed platforms to dramatically simplify these complex computing and data acquisition problems.

Cadence Low Power Solution - RTL to GDSII Low Power Design

Low-power design used to be an afterthought. Today, however, we need to consider power throughout the entire design cycle - from RTL all the way through GDSII. And, we can have significant impact on overall power consumption with optimizations at just about every stage. In this episode of Chalk Talk, Amelia Dalton chats with Pete Hardee of Cadence about a holistic approach to low-power design.

It's an Analog World After All

It's an analog world out there. And, while most microcontrollers offer terrific features in the digital and software domain, Microchip has a new family of MCUs with Intelligent Analog capabilities that can make a huge difference in connecting your design to the real world. In this episode of Chalk Talk, Amelia Dalton talks to Alexis Alcott of Microchip about harnessing the power of Intelligent Analog in MCU design.

Smartphone and Tablet Accessory Design

In this episode of Chalk TalkHD Amelia Dalton talks to David Flowers from Microchip about creating tablet and smartphone accessories - and how it just may be easier than you think...

Getting Started Using Kintex-7 FPGAs for DSP

In this episode of Chalk TalkHD Amelia chats with Tom Hill of Xilinx about their new Kintex-7 DSP development kits that will finally get you onto the rocket-coaster of FPGA-powered DSP.

Digital Predistortion for Base Station Power Amplifiers

In this episode of our new Chalk TalkHD series, Amelia Dalton talks to Todd Nelson from Linear Technology about how digital predistortion (DPD) can be used to save millions of dollars worth of power in base station designs. DPD is simple to apply, and has a dramatic impact on the power amplifier - the most power-hungry part of modern base stations. In this Chalk TalkHD you'll hear how DPD works and how you can apply it to your next design.

latest papers and content

Ethernet in Cars

In this week's Whiteboard Wednesdays video, Arthur Marris introduces the next big thing in the Ethernet space—Ethernet in cars. With its high data rate, lightweight cabling, and distributed networking capabilities, as well as the fact that it is an interoperable open standard and works well with TCP/IP, Ethernet is ideal for addressing many of the challenges facing automotive engineers.

What is Electrically Aware Design?

For years, layout tools have focused on the pins and wires, the "froms" and "tos", the segments and nets - without considering that they were really creating a complex electrical circuit. Today, however, the electrical properties of our layout is critical, and issues like parasitic resistance and capacitance can have a dramatic effect on our final design. In this episode of Chalk Talk, Amelia Dalton chats with John Stabenow of Cadence about electrically-aware design with Cadence's Virtuoso.

Five Ways to Build Flexibility into Industrial Applications with FPGAs

System complexity continues to increase in industrial designs such as communications, motor control, I/O modules and image processing. Read how FPGAs offer the ability to integrate an entire SoC at a lower cost compared to discrete MCU, DSP, ASSP, or ASIC solutions. Whether used as a coprocessor or SoC, FPGAs offer the following advantages for your industrial applications: · Design integration to simplify and reduce cost · Reprogrammability to adapt industrial designs to evolving protocols · Performance scaling to meet your system requirements. · Obsolescence protection through long FPGA life cycles and device migration

Advanced System Management with Analog Non-volatile FPGAs

A system management device is critical to the successful power up, configuration, maintenance and power down of the system. As system complexity increases, the requirements of these devices are growing and features such as instant-on, analog capability, and flexibility are crucial. Read how a robust system management design incorporates a wide variety of tasks in both the analog and digital domain including power rail management, environmental condition management, and analytics for diagnostics and prognostics.

Wireless Base Station ZUC Block Cipher Implementation on Zynq SoCs

The Xilinx Zynq®-7000 All Programmable SoC provides a flexible platform that offers programmability for evolving technologies like LTE and new standards including, but not limited to, the ZUC algorithm. This white paper illustrates the advantages of the Zynq SoC-based design methodology using the Vivado® Design Suite, which facilitates an optimal hardware/software partitioning of the system functionality for better performance.

Enabling High-Speed Radio Designs With Xilinx All Programmable FPGAs and SoCs

This white paper describes the capabilities of Xilinx® 7 series All Programmable FPGAs and SoCs to implement high-clock-rate signal processing functionality typically used by the datapath of digital radio applications.

Mastering the Magic of Multi-Patterning

Multi-patterning technology was introduced at the 20 nm node to overcome lithographic limitations in current IC manufacturing processes. Successfully implementing multi-patterning compliance in the IC design and verification flow requires a thorough understanding of multi-patterning techniques and their impact on your design. Learn what multi-patterning is, why you need it, and how Calibre® Multi-Patterning software can help you effectively and efficiently incorporate multi-patterning into your leading-edge designs.

Improving Design Reliability by Avoiding Electrical Overstress

With the advent of more complex design requirements and greater variability in operating environments, electrical overstress (EOS) is one of the leading causes of IC failures across all semiconductor manufacturers. The use of multiple voltages increases the risk of EOS, so IC designers need to increase their diligence to ensure that thin-oxide digital transistors do not have direct or indirect paths to high-voltage portions of the design. The techniques for ensuring circuit reliability must evolve, even for established technologies.

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

Cadence Allegro PCB Design Solution

Allegro PCB Designer is a scalable, proven PCB design environment that addresses technological and methodological challenges while making the design cycles shorter and predictable. Read how Allegro PCB Design Solution can manage complexity for faster, more cost-effective implementations.

Cadence and IBM: Customer Success Story

“The Cadence solution enables us to enter up to 99 percent of signals in table format, which, along with improved analytics and a unique integrated environment, reduced our PCB development time by 80 percent.” Learn why Gisbert Thomke, a group leader at IBM is able to say that and how exactly the company accelerates large-scale PCB system design using unique cadence multi-style design entry solution.

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Implementing Floating-Point DSP in an FPGA

Are you finding it challenging to efficiently implement floating-point digital signal processing (DSP) algorithms? Learn how Altera’s new floating-point design flow makes it easy and enables your designs to achieve high performance and efficiency.

MAX Series Configuration Controller Using Flash Memory

Altera’s flash memory configuration controller provides an alternative configuration solution for high-density FPGA-based designs. With the flexibility to use a bigger flash memory to store more configuration data, designers can implement the flash memory controller in MAX series devices for use in Stratix series, Arria series, and Cyclone series FPGAs. Configuration bitstream sizes are increasing with the higher-density FPGAs, which require larger devices to store and configure data.

Integrating 100-GbE Switching Solutions on 28-nm FPGAs

Because today’s single-chip-based architectures are unable to meet this demand for increased bandwidth and complexity, there is a need to develop efficient algorithms and switching architectures to meet the high-speed network requirements. Stratix V FPGAs enable hardware designers to integrate true 100-GbE components for next-generation switches and routers that ensure QoS while balancing the distribution of data through the system.

Pulsed RF Operation of Microsemi GaN RF Power Transistors

This paper explains the pulsed RF operation of Microsemi pulsed GaN HEMT RF power transistors using as an example the 1011GN-700ELM 1030MHz Mode-S Enhanced Message Length (ELM) avionics device. General descriptions are presented detailing both the pulsed gate bias operation and the bias sequencing operation of the “pulser” circuit used on the Microsemi evaluation test fixtures. This pulser circuit is also successfully implemented on all Microsemi pulsed common source class AB GaN device evaluation test fixtures for both pulsed avionics system and radar systems, from L-Band through C-Band and can be extended up to X-Band and Ku Band. A general description of the 1011GN-700ELM RF input and output circuit board design is also provided. Finally, 1011GN-700ELM pulsed RF device performance will be presented demonstrating the use of the pulser circuit in a test fixture.

Increasing Efficiency with Hard Memory Controllers in Low-Cost 28 nm FPGAs

With the hard memory controller (HMC) in Altera® Cyclone® V FPGAs, designers can maximize efficiency and flexibility, thereby achieving low power and low cost for their systems and applications. Check out the whitepaper to learn more.

Reducing Power Consumption and Increasing Bandwidth on 28nm FPGAs (REVISED)

Lower power consumption and higher bandwidth are the dominant requirements in designing next-generation high-end applications. The trend is for higher bandwidth in the same footprint at the same or lower power and cost as the Internet goes mobile. The march to 40G and 100G systems is underway to support this ever-growing bandwidth demand. Fierce competition is driving down prices. Space constraints abound, and cooling solutions often dominate the power budget, sometimes up to twice the power consumption of the electronics. Altera’s 28-nm FPGAs address these challenges through leading-edge technological innovation, integration, and reduced power consumption.

New Approach to Manage Electrical Complexity

Today's competitive and challenging environment, thought-leaders are recommending a shift to systems engineering. Using a systems engineering approach could help OEMs maintain product quality, reduce costs, manage change, and achieve time to market. This paper talks about applying systems engineering principles using the Capital tool suite to address these issues.

Understanding Metastability in FPGAs

Metastability is a phenomenon that can cause system failure in digital devices when a signal is transferred between circuitry in unrelated or asynchronous clock domains. This paper describes metastability in FPGAs, explains why the phenomenon occurs, and discusses how it causes design failures. The MTBF due to metastability indicates whether steps should be taken to reduce the chance of such failures. This paper explains how MTBF is calculated, and how both vendors and designers can increase it.

Why Cadence Verification IP (VIP) Is a Smart Choice for SoCs

In this week's Whiteboard Wednesdays episode, Tom Hackett discusses why over 500 customers consider Cadence Verification IP to be the S.M.A.R.T. choice when looking to verify their SoC designs.

Enabling FPGA Plug-and-Play Design with the AXI-4 Common Interconnect

This video offers details of Xilinx support for the AXI-4 Common Interconnect and highlights the benefits of increased designer productivity, greater IP availability, and extended flexibility to achieve performance and system goals. Using the Xilinx Targeted Design Platforms to illustrate these benefits, Xilinx technical experts describe how support for the AXI-4 Common Interconnect is the cornerstone for the move to FPGA Plug-and-Play design.

Putting Low Power and Flexibility Where It Matters Most: Handheld Portable Applications

In the short span of three decades, electronics have not only proliferated in our world, but have also gotten smaller and more portable. The march of Moore’s Law has brought portability to the consumer, industrial, military, medical and other markets. Download this whitepaper to learn about Actel solutions for handheld portable applications.

Solutions for Mixed-Signal IP, IC, and SoC Implementation

Traditional mixed-signal design environments, in which analog and digital parts are implemented separately, are no longer sufficient and lead to excess iteration and prolonged design cycle time. Modern mixed-signal designs require new flows that maximize productivity and facilitate close collaboration among analog and digital designers. This paper outlines mixed-signal implementation challenges and focuses on three advanced, highly integrated flows to meet those challenges.

ARM and Cadence Help SoC Designers Achieve Power, Performance, and Area Goals

William Orme, Strategic Marketing Manager at ARM, and Steve Brown, Director of Product Marketing at Cadence, describe the collaboration and use of the Cadence(r) Interconnect Workbench with ARM’s CoreLink(r) System IP to help SoC designers achieve their power, performance and area goals.

Xilinx at NAB 2014 | intoPIX Tico

Jean-Baptiste Lorent, Product & Marketing Manager at intoPIX, describes the TICO lightweight compression that is ideal for converting HD workflows to 4K/8K workflows.

Power Consumption at 40 and 45nm

At 40 and 45 nm process nodes, power quite often becomes the primary factor for FPGA selection. This white paper details how Xilinx designed for low power in its new Spartan®-6 and Virtex®-6 FPGA families, achieving dramatic power reductions over previous generation devices.

Streamline Your Video Processing Apps with Design Examples

Wouldn’t it be great if you could develop your video processing applications faster? You can with a complete suite of ready-to-use video processing functions. These functions are ready to be dropped into your design and connected through open Avalon® Streaming interfaces. Watch this 5-minute video for a demo that shows you a low-cost touch screen-based development kit running two design examples based on these functions.

An Introduction to Rigid-Flex PCB Design Best Practices

More designers increasingly face project requirements for densely populated electronic circuits including pressures to reduce manufacturing times and costs. To meet these requirements, design teams have increasingly turned to 3D rigid-flex circuits to meet their project’s performance and production requirements.

8 Reasons to Use FPGAs in IEC 61508 Functional Safety Applications

FPGAs are increasingly replacing electronic components used for industrial applications, thus international standards like the IEC 61508 have to support these evolving technology trends if they want to keep their relevance. This white paper gives developers eight simple reasons why FPGAs should be chosen in their IEC 61508 functional safety project versus standard microcontrollers or DSPs.


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