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It’s Easy to Protect Your Embedded System from Theft

If you have invested years and millions of dollars in the design of an embedded system (and in the creation of the Intellectual Property, or IP, that goes along with the design) it can be of critical importance to protect that system from unauthorized duplication or theft. After all, it’s much easier to steal something as complex as a multi-million gate FPGA design than to create, debug, and test it. The protection of an embedded system that uses FPGAs, is particularly relevant since FPGAs have become the platforms of choice for innovation.

Understand USB Controllers and Their Performance Specs

In this week's Whiteboard Wednesdays video, Jacek Duda provides an informative overview of USB controllers and the potential performance that can be achieved. He also discusses specs for USB 2.0 and USB 3.X in detail.

Rigid-Flex and Embedded Components

These days, flexibile circuit boards are making their way into the mainstream. Rigid-flex design gives us all kinds of new capabilities in form factor, as well as the opportunity to replace expensive and unreliable cables and connectors. But, how do you handle rigid-flex PCB design in your layout tools? In this episode of Chalk Talk, Amelia Dalton chats with Altium's Ben Jordan about rigid-flex design in Altium Designer - and how you can use those same capabilities for embedded components as a bonus!

Enabling the Internet of Things: Introducing Atmel SAM D20 Cortex M0+ Family

Your design needs to connect to the Internet of Things (IoT), doesn't it? Connecting your device to the rapidly expanding IoT opens up a wide world of potential new capabilities. In this episode of Chalk Talk, Amelia Dalton chats with Andreas Eieland (Atmel) about some amazing new devices that can dramatically simplify the task of getting your next design into the IoT party.

FPGA Product Support and EOL as Past Performance Indicators

This white paper presents the factors that lead to product obsolescence decisions made by FPGA vendors and how you can use this knowledge to craft obsolescence risk mitigation plans. This paper also introduces the idea of exercising Past Performance Assessments of FPGA vendors as both a risk and cost factor in making FPGA selection in military system design.

Xilinx Broadest Cost Effective All Programmable Low-end Portfolio

This generation of all programmable, cost-sensitive applications has reached new levels of sophistication and diversity of requirements. Low cost systems in the consumer, automotive, industrial, medical, and communications space may need a programmable logic device with high serial bandwidth, or for advanced processing, or may simply need bridging functionality and little else. Commonly termed the “low-end” market due to the devices’ relatively low cost and density, these platforms provide varying levels of system integration, performance, and power. They may perform critical tasks such as video analytics or packet processing, or simply expand a system’s I/O connectivity to peripheral devices.

How To Save 75% on Your Next ASIC Design

Do you think developing a custom mixed-signal chip for your application is beyond your team's reach? Too expensive, complicated, and risky? Think again! In this episode of Chalk TalkHD Amelia chats with Reid Wender of Triad Semiconductor about how you can dramatically reduce design costs and complexity - bringing that custom chip design within reach. In part one of our three-part Chalk TalkHD series, Amelia and Reid tell you how to save 75% on your design.

Industrial Temperature Measurement Solutions

Many industrial designs need data from sensors such as temperature probes. But, getting from the analog world of probe signals to the digital world where the magic happens can be a tedious and tricky process. In this episode of Chalk Talk, Amelia Dalton talks with Sean Long of Maxim Integrated about an easy way to connect up sensors such as temperature probes in your next industrial design.

Timing Closure Made Easier with Stylus

In this episode of Chalk TalkHD Amelia chats Andy Caldwell (Tabula) about putting an end to the oppressive reign of timing closure terror. Tabula’s Spacetime architecture - it turns out - besides giving us crazy performance for our high-bandwidth designs - also makes timing closure drop-dead easy.

Market-Specific Custom IC Solutions

When it comes to custom IC design, one size most definitely does not fit all. Different applications call for specialized IP, tools, and even semiconductor processes. But, sorting through the options can be a daunting process. In this episode of Chalk Talk, Amelia Dalton chats with Pavel Klinger from GLOBALFOUNDRIES about market-specific solutions that can get your product to market faster and with lower risk than ever.

Solving the 100Gbps Challenge with ABAX2

What do you do when plain-old FPGAs leave too much on the table to handle your next bandwidth challenge efficiently? In this episode of Chalk TalkHD Amelia chats with Christian Plante (Tabula) about Tabula's new ABAX2 devices - based on their innovative Spacetime architecture. ABAX2 is fabricated on the latest Intel 22nm Tri-Gate technology, and can give you an enormous advantage in your next 100G design.

Verify Design Performance with PADS Best-in-Class Simulation and Analysis

It really isn't important to simulate your PCB design - as long as you don't care about re-spins, signal integrity, cost... OK, actually, there are many good reasons to simulate your board. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about simulating your board design using PADS. It may make you re-think your board design strategy.

How to Design a Sigma Delta Mixer Circuit

In parts 1 & 2 of this 3-part Chalk Talk series, we talked about how Triad Semiconductor can save you 75%, or even as much as 99% in your next mixed-signal ASIC design. But, what good is savings if you don't know what you can design with it? In this third episode of our 3-part Chalk Talk series, Amelia and Reid Wender of Triad Semiconductor have fun taking ViaDesigner out for a spin - designing a sigma delta mixer.

Fast, Efficient RTL Debug for Programmable Logic Designs

In a typical FPGA design flow, most designers work from a written specification that contains architectural level drawings defining the major logic blocks, interfaces, and busses. The design manager begins to partition functionality based on the diagrams and to assign development based on the block’s functional descriptions. Each block is coded individually and may be simulated in a block-specific test bench. The team assembles the blocks into a device-level file where the ports are pins on the target device. The design is then ready to be compiled for simulation initiating the debug phase of development: Simulation followed by hardware debug.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

New Approaches to Hardware Acceleration Using Ultra Low Density FPGAs

Ask system designers to list the problems they face – it doesn’t matter whether they’re building mobile consumer, automotive, industrial, medical or scientific applications – and inevitably they’ll mention optimizing host processor performance. It’s hardly surprising. The event-driven architecture of these MPUs allows them to multitask and address new priorities as they occur. But as the number of I/O continues to rise, it also places escalating demand on bandwidth. Tasked with managing a wider array of I/O as well as other system-wide command and control functions, today’s host MPUs must remain operational for longer periods of time, thereby consuming precious power and compute resources.

Maximize Your Power and Efficiency with PADS Interactive Placement and Routing

For the engineer doing desktop PCB layout, efficiency is important. You don't want to waste precious time fighting with your PCB tool, and you don't want to end up with lousy results because you and your tool weren't getting along. Mentor Graphics PADS provides an efficient, high-productivity interactive placement and routing environment that lets you get great results quickly. In this episode of Chalk Talk, Amelia Dalton talks to Jim Martens of Mentor Graphics about interactive layout using PADS.

OTN Transport of Baseband Radio Serial Protocols in C-RAN Architecture for Mobile Network Applications

This joint white paper by MTI Mobile and Altera presents a proof of concept implementation of digital baseband radio data transport over Optical Transport Network (OTN) compliant to 3GPP Long Term Evolution – Advanced (LTE-A) standard, which enables us to exploit the benefits of Cloud Radio Access Network (C-RAN) architecture. The purpose of this paper is to demonstrate that data transport between the MTI Radiocomp’s baseband module and a remote radio module over an OTN-compliant mapper from Altera is compliant to Common Public Radio Interface (CPRI) and to the OBSAI interface protocols.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

How To Save 99% on Your Next Mixed Signal ASIC Design (part 2 of a 3-part series)

In part 1 of this 3-part series, we talked about how you can save 75% on your next mixed-signal chip design - which was great, but we think we can do better than that. In this episode of Chalk TalkHD Amelia chats with Reid Wender of Triad Semiconductor about how you can dramatically reduce design costs and complexity even more. In this second epsiode of our 3-part Chalk TalkHD series, Amelia and Reid tell you how to save up to 99% on your design.

It's the Software, Silly! - Success with FPGA-based Prototyping

Software is becoming a larger and larger part of our system-on-chip (SoC) designs. It is critical that we be able to begin developing and debugging software as early as possible in the design cycle. But, the hardware part of today's complex designs takes months to stabilize. In this episode of Chalk Talk, Amelia Dalton talks with Juergen Jaeger of Cadence about the tight relationship between software and emulation and how you can achieve success in your SoC design with a comprehensive emulation strategy.

chalk talks

Enabling New Applications with NFC Connectivity and Energy Harvesting

In this episode of Chalk TalkHD Amelia chats with Greg Proehl (STMicroelectronics) about the basics of NFC technology, and they explore some interesting NFC applications as well as cool and innovative new NFC solutions from ST - including one with energy harvesting capability.

Cadence Tempus Timing Signoff Solution

Achieving timing closure for signoff can be a daunting challenge in today's complex designs. Meeting timing under all conditions - with the certainty required for signoff - is a complex and demanding task. In this episode of Chalk Talk, Amelia Dalton talks to Ruben Molina of Cadence Design Systems about the special challenges of signoff timing closure, and Cadence's new Tempus timing analysis tool.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

Adding Wi-Fi to Your FPGA Design - Building a Connected Device

In the first episode of our new Chalk TalkHD series, Amelia Dalton talks to Bob Potock from Altium as they add Wi-Fi to an FPGA-based embedded system.

It's an Analog World After All

It's an analog world out there. And, while most microcontrollers offer terrific features in the digital and software domain, Microchip has a new family of MCUs with Intelligent Analog capabilities that can make a huge difference in connecting your design to the real world. In this episode of Chalk Talk, Amelia Dalton talks to Alexis Alcott of Microchip about harnessing the power of Intelligent Analog in MCU design.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

Timing Closure in FPGA Designs Made Easy with PlanAhead

In this episode of Chalk TalkHD Amelia chats with Frederic Rivoallon of Xilinx and they attempt to unravel the mysteries of timing closure and reveal that yes, you can get timing closure right the first time in your next design.

100G Ethernet Packet Parsing with Spacetime

Designing 100G Ethernet is a daunting challenge. Timing, power, latency, and throughput all fight with each other, and it's easy to fall into a design trap with a solution that doesn't offer a good compromise. In this episode of Chalk Talk, Amelia Dalton chats with Parsun Raha about the challenges of 100G (and beyond), and how those conflicting design goals can be met by Tabula's innovative Spacetime architecture.

latest papers and content

Understand USB Controllers and Their Performance Specs

In this week's Whiteboard Wednesdays video, Jacek Duda provides an informative overview of USB controllers and the potential performance that can be achieved. He also discusses specs for USB 2.0 and USB 3.X in detail.

Comparing 3D Memory Solutions and Their Market Applications

In this week's Whiteboard Wednesdays video, Scott Jacobson completes his three-part series on the Memory Wall with a discussion on the different 3D memory solutions available today and their market applications. You may recall that in the first segment, Scott examined how CPU performance outstrips memory transfers, and discussed options available to system designers, such as 2D solutions. In the second part of this series, Scott took a closer look at 2D memory solutions like EMMC 5.0, UFS, and DDR4.

How IP Enhances Hosted Virtual Desktops

In this week’s Whiteboard Wednesdays, Charles Qi introduces an emerging new application called Hosted Virtual Desktop, which supports increasingly mobile workers who want to use any smart, connected device to access corporate data resources. Charles goes into detail about how Cadence IP can help expand the application to help businesses make mobile workforces more efficient.

Artix-7 FPGA Transceiver: The Industry's Most Capable Transceiver in a Low-End Device

In this video you’ll see the FPGA industry’s only low end transceiver solution—the Artix-7 FPGA transceiver—that provides auto-adaptive equalization, 2D Eye Scan, and IBIS-AMI simulation models to simplify high speed serial design for cost-sensitive applications.

Xilinx Broadest Cost Effective All Programmable Low-end Portfolio

This generation of all programmable, cost-sensitive applications has reached new levels of sophistication and diversity of requirements. Low cost systems in the consumer, automotive, industrial, medical, and communications space may need a programmable logic device with high serial bandwidth, or for advanced processing, or may simply need bridging functionality and little else. Commonly termed the “low-end” market due to the devices’ relatively low cost and density, these platforms provide varying levels of system integration, performance, and power. They may perform critical tasks such as video analytics or packet processing, or simply expand a system’s I/O connectivity to peripheral devices.

New Approaches to Hardware Acceleration Using Ultra Low Density FPGAs

Ask system designers to list the problems they face – it doesn’t matter whether they’re building mobile consumer, automotive, industrial, medical or scientific applications – and inevitably they’ll mention optimizing host processor performance. It’s hardly surprising. The event-driven architecture of these MPUs allows them to multitask and address new priorities as they occur. But as the number of I/O continues to rise, it also places escalating demand on bandwidth. Tasked with managing a wider array of I/O as well as other system-wide command and control functions, today’s host MPUs must remain operational for longer periods of time, thereby consuming precious power and compute resources.

Using Low Cost, non-volatile PLDs in System Applications

The system market is comprised of applications in telecom infrastructure, computing, high end industrial and high end medical. Power supply sequencing, voltage and current monitoring, bus bridging, voltage level translation, interface control, and temperature measurement are typical board functions found in these applications. System designers are faced with continual pressure to meet their development schedules, and need to implement designs with minimal effort and risk while maintaining maximum flexibility. By using a programmable-based approach instead of several discrete devices or Application Specific Standard Products (ASSPs), designers can accelerate their time-to- market, address system cost and space reduction, and ensure a high level of product differentiation.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Intelligently Expanding Microprocessor Connectivity Using Low-cost FPGAs

Whether they be CPUs, microprocessors or microcontrollers, microprocessors are an indispensable component in modern electronic system design. However, as systems become more complex and host a wider array of features and user interfaces, system architects using mid-range microprocessors in particular typically face three key challenges connecting the microprocessor, or microprocessors, they are using to the rest of their system: implementing more than 150 general purpose I/Os (GPIO), finding cost effective solutions in the 100 to 150 GPIO range, and matching available I/O peripherals with system needs. These challenges can easily be overcome with the use of FPGAs (field programmable gate arrays), which over the past 10 years have seen a significant reduction in cost and power consumption, making them ideal for a wide range of high- volume, low-cost applications including mobile.

Security Aspects of Lattice Semiconductor iCE40 Mobile FPGA Devices

Product piracy is of strong concern to major companies around the world. R&D costs are very high for leading companies. Therefore, companies plan to recoup these R&D costs by sale of their proprietary products. If pirates are able to steal or copy the final design, or countermand the security systems of these proprietary products, the market will become flooded with low cost alternatives. As a final consequence, major companies will find themselves unable to recover their high development costs, and will lose valuable profits.

Vivado IP Integrator - Tech Packet

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design.

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The Industry's First 20nm and UltraScale FPGAs and 3D ICs

The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system level performance for the most demanding applications.

Streaming Multichannel Uncompressed Video in the Broadcast Environment

Designing video equipment for streaming multiple uncompressed video signals is a new challenge, especially with the demand for high-definition video streams. This white paper examines how a multichannel streaming PCIe DMA controller and other “building block” IP cores are combined within a Cyclone IV GX FPGA to support SD- and HD-SDI applications using an open-source video packet streaming-format protocol such as those used in non-linear editors, video servers, and video-capture applications.

STMicro Shortens Turnaround Time with Cadence's Mixed-Signal Solutions

STMicroelectronics relies on mixed-signal solutions for its Smart Power Technologies. As Livio Frantantonio explains in this video, STMicro needed to increase productivity and quality of results while shortening its turnaround times. The company found its answer in Cadence's mixed-signal solutions, including Virtuoso® Mixed-Signal Flow. Watch this video to learn how STMicro benefited from using the Cadence Unified Mixed-Signal Methodology.

Extending Transceiver Leadership at 28nm

As next-generation applications and systems continue driving up I/O bandwidth demands, transceivers are evolving to meet these requirements. The latest-generation transceivers deliver the highest data rates, at up to 28 Gbps, at the lowest power for applications such as 100 Gigabit Ethernet systems. In this 40-minute webcast, you'll get a close look at key transceiver capabilities in our 28-nm Stratix® V FPGAs.

Providing Battery-Free, FPGA-Based RAID Cache Solutions

RAID adapter cards are critical data-center subsystem components that ensure data storage and recovery during power outages. Battery-backed designs have hazardous waste disposal, shelf life, and maintenance issues, but recent advances in FPGA and flash-memory technologies support lower power memory backup designs that are powered by ultra capacitors. This paper provides an overview of the supporting component technologies that support such environmentally-friendly data recovery solutions.

Supercharging Design Performance and Productivity with Altera FPGAs and Best-in-Class IP

This white paper examines how Altera's optimized and verified intellectual property (IP) blocks can simplify your design, reduce design issues, and shorten time to market. It also explains how Altera's Generation 10 FPGAs enables broad portfolio of complex IP-the broadest portfolio in the industry-to achieve a 50 percent reduction in size while achieving twice the performance of current devices.

All Programmable Abstractions Video

New All Programmable Abstractions initiative improves productivity of hardware designers and empowers systems and software developers to directly leverage Xilinx All Programmable devices.

Next Generation System Design – Platforms versus Tool-Chains

This paper will enumerate the benefits of a platform-based system design approach. The original electronic design process built by linking tools together has remained largely unchanged for decades (i.e. tool-chains). A layered platform architecture unifies PCB, FPGA and embedded software development into one application. At the foundation is a unified data model that enables numerous data management benefits including versioning and ECO management. Companies switching to a platform based design process are doubling their productivity as compared to traditional tool-chains.

A Flexible Solution for Industrial Ethernet

This white paper describes the use of FPGAs to deliver a multi-standard Industrial Ethernet capability from a single printed circuit board implementation. The benefits of FPGA implementation are described and an overview of the FPGA development flow, tools, and technology used to create a universal but easy to maintain solution is given. Since its conception by Xerox in the 1970s and standardization as IEEE 802.3 in 1983, Ethernet has become the de facto standard for computer communication.

Expect a Breakthrough Advantage in Next-Generation FPGAs

A product strategy that uses a tailored approach drawing upon using different process technologies, architectures, and integration options targeted to different applications will give hardware architects the best possible choices and solutions. This white paper covers examples of why telecommunication bandwidth and the infrastructure behind it is driving FPGA capabilities, business challenges of ASICs and ASSPs, and how a tailored approach for programmable logic devices (PLDs) provide a leap in FPGA capabilities. This paper also outlines Altera’s generation 10 portfolio of next-generation FPGAs and SoCs that seeks to provide a breakthrough in capabilities and advantages across a variety of different applications.

3 Reasons to Use FPGAs in Industrial Applications

Gone are the days when FPGAs were used for glue logic or simple I/O expansion. Today's industrial applications are reaping benefits with FPGAs integrated into the designs as coprocessors or even system-on-a-chip (SoC) solutions.

Actel FPGAs for Handheld Portable Applications

The portable electronics market is booming, and the continuing demand for smaller, more portable devices poses design challenges as end-users want more features, improved performance plus longer battery life. Actel’s nonvolatile flash FPGAs are unique in their ability to meet all the demands of the portable electronics designer: low active and static power consumption, small footprint packages, design security, higher integration, and live at power-up operation.

Putting Low Power and Flexibility Where It Matters Most: Handheld Portable Applications

In the short span of three decades, electronics have not only proliferated in our world, but have also gotten smaller and more portable. The march of Moore’s Law has brought portability to the consumer, industrial, military, medical and other markets. Download this whitepaper to learn about Actel solutions for handheld portable applications.

Achieving Low BER Across 10+ Gbps Serial Links

As serial data rates increase beyond 10 Gbps to address high-bandwidth applications (e.g., 40G/100G systems), board design challenges grow as well. Ensuring statistical reliability of a serializer/deserializer (SERDES) channel requires careful board design, as well as advanced silicon capabilities to handle losses due to PCB material properties and reflections due to discontinuities in the channel.

How To Save 99% on Your Next Mixed Signal ASIC Design (part 2 of a 3-part series)

In part 1 of this 3-part series, we talked about how you can save 75% on your next mixed-signal chip design - which was great, but we think we can do better than that. In this episode of Chalk TalkHD Amelia chats with Reid Wender of Triad Semiconductor about how you can dramatically reduce design costs and complexity even more. In this second epsiode of our 3-part Chalk TalkHD series, Amelia and Reid tell you how to save up to 99% on your design.

Xilinx DSP Targeted Design Platforms Deliver Performance, Price, Power, and Productivity

Digital signal processing (DSP) design starts have surpassed every other segment of the processing arena. Consequently, the demand for differentiated value in every aspect of DSP design has never been higher, increasing pressure on the teams tasked to build winning designs in record time. Xilinx conceived the Targeted Design Platform to address this challenge—the necessity to do more with less, to remove risk wherever possible, and to differentiate in order to excel.

User-Customizable ARM-Based SoC FPGAs for Next-Generation Embedded Systems

This white paper discusses Altera’s programmable system-on-chip (SoC) approach to ARM-based embedded system implementation. The single-chip approach can be of particular value to embedded systems developers facing stringent time-to-market, cost, performance, design reuse, and longevity requirements.

Architecture Matters: Choosing the Right SoC FPGA for Your Application

SoC FPGAs are a powerful new class of programmable devices that are applicable to a wide range of electronic designs. This white paper discussed a number of criteria to select the best SoC FPGA for your particular application, including system performance, design reliability and flexibility, system cost, power consumption, future product roadmaps, and the important role that development tools will play into the success of these SoC FPGAs.


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