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Addressing Next-Generation Memory Requirements Using Altera FPGAs and HMC Technology

The white paper describes Altera(r) technology leadership in the serial memory interoperability space and describes the underlying hardware platform and controller architecture used to carry out a successful interoperability between Stratix(r) V FPGA and the HMC device. The document also includes real system-level examples where HMC solution provides an alternative solution to conventional memory-based solutions.

Allegro FPGA System Planner

The Cadence Allegro FPGA System Planner addresses the challenges that engineers encounter when designing one or more large-pin count FPGAs on the PCB board. By replacing manual error-prone processes with automatic pin assignment synthesis, this unique placement-aware solution eliminates physical design iterations while speeding optimum pin assignment.

Cadence Low Power Solution - RTL to GDSII Low Power Design

Low-power design used to be an afterthought. Today, however, we need to consider power throughout the entire design cycle - from RTL all the way through GDSII. And, we can have significant impact on overall power consumption with optimizations at just about every stage. In this episode of Chalk Talk, Amelia Dalton chats with Pete Hardee of Cadence about a holistic approach to low-power design.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

Aldec Active HDL Datasheet

Active-HDL is an integrated FPGA Design and Simulation solution, with design entry, a high-performance mixed-language simulator and an easy-to-use, multi-vendor FPGA flow manager. Active-HDL has interfaces to over 80 leading EDA tools, making it the most powerful environment. Check out the top features and product configurations to see if Active-HDL is right for you.

It's an Analog World After All

It's an analog world out there. And, while most microcontrollers offer terrific features in the digital and software domain, Microchip has a new family of MCUs with Intelligent Analog capabilities that can make a huge difference in connecting your design to the real world. In this episode of Chalk Talk, Amelia Dalton talks to Alexis Alcott of Microchip about harnessing the power of Intelligent Analog in MCU design.

Protium Rapid Prototyping Platform

Building a robust prototype involves a lot more than just throwing a bunch of big FPGAs on a board or in a box. In fact, success of a prototype is a lot more about the system surrounding the boards - the tools, design flow, and IP that make the whole thing come up easily and work smoothly. In this episode of Chalk Talk, Amelia Dalton talks to Juergen Jaeger of Cadence about the new Protium Rapid Prototyping Platform from Cadence, and how it can simplify your prototyping process.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

Battery Management Solutions

Designing battery-powered systems can be challenging. In addition to power and form-factor considerations, today's batteries require sophisticated charging and monitoring for maximum safety, life, and performance. In this episode of Chalk Talk, Amelia Dalton chats with Richard DelRossi of Texas Instruments about battery management solutions that can dramatically simplify your next battery-powered design while adding important monitoring capabilities to your device.

Leveraging MIPI D-PHY-based Peripherals in Embedded Designs

Embedded systems designers face an ongoing dilemma. On the one hand they need to drive down systems costs. On the other they cannot exploit manufacturing economies of scale because their systems are targeted at relatively narrow, low volume applications. While high volume consumer markets offer components capable of performing similar tasks at much lower cost, embedded designers are restricted from taking advantage of those components by their systems’ reliance on highly specialized, legacy interfaces optimized for the embedded environment.

Industrial Temperature Measurement Solutions

Many industrial designs need data from sensors such as temperature probes. But, getting from the analog world of probe signals to the digital world where the magic happens can be a tedious and tricky process. In this episode of Chalk Talk, Amelia Dalton talks with Sean Long of Maxim Integrated about an easy way to connect up sensors such as temperature probes in your next industrial design.

Modernizing System Development

Allowing disconnected development and waiting until the latest program stages to perform systems integration and connect all the pieces is a high risk situation, yet one all too common in today’s product realization process. Bringing domain expertise together as appropriate throughout a project’s development process is imperative for project success.  This paper explores a more modern approach to system development built on a Model Driven Development (MDD) approach.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Routing Interfaces Quickly & Efficiently on PCBs

In today's PCB designs, interfaces such as DDR pose major challenges for layout. Issues like timing and signal integrity can be tricky for even the most experienced designer. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about routing those tricky bits using a combination of automatic and manual routing techniques.

Xilinx and Open-Silicon HMC Memory Solution

Watch a demonstration of the industry's first available 12.5 Gb/s Hybrid Memory Cube (HMC) interface using the Xilinx Virtex®-7 FPGA. See how this solution provides superior memory bandwidth for your application using HMC technology, Virtex-7 FPGA, and Open-Silicon IP.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

Simulation Key to Automotive Challenges

This paper describes a new virtual prototyping environment that allows system integration to begin before physical hardware can be made available, a valuable commodity in today’s complex automotive system design process.  This new technology gives designers powerful tools for managing mechanics, electronics, software, and controls in one system with the capability to integrate the significant intersections between them.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Using Low Cost, Non-volatile PLDs in System Applications

The system market is comprised of applications in telecom infrastructure, computing, high end industrial and high end medical. Power supply sequencing, voltage and current monitoring, bus bridging, voltage level translation, interface control, and temperature measurement are typical board functions found in these applications. System designers are faced with continual pressure to meet their development schedules, and need to implement designs with minimal effort and risk while maintaining maximum flexibility. By using a programmable-based approach instead of several discrete devices or Application Specific Standard Products (ASSPs), designers can accelerate their time-to- market, address system cost and space reduction, and ensure a high level of product differentiation.

chalk talks

Hardware/Software Co-Verification of ARM Processor-Based Designs

In this episode of Chalk TalkHD Amelia chats with Lauro Rizzatti of EvE about the latest in emulation technology and explains how you can use emulation to dramatically accelerate software development, which is becoming the most time-consuming part of SoC design.

Verification Methodologies (Made Easy)

Most FPGA designers don’t know much about formal methodologies for verification. It’s too bad, because today’s complicated FPGA designs can really take advantage of standardized methodologies like UVM. In this episode of Chalk TalkHD Amelia and Jerry Kaczynski (Aldec) are going to unscramble the anagrams and get you on your way to understanding and harnessing the power of universal verification methodologies - so you can start applying them to your next design.

How to Design a Sigma Delta Mixer Circuit

In parts 1 & 2 of this 3-part Chalk Talk series, we talked about how Triad Semiconductor can save you 75%, or even as much as 99% in your next mixed-signal ASIC design. But, what good is savings if you don't know what you can design with it? In this third episode of our 3-part Chalk Talk series, Amelia and Reid Wender of Triad Semiconductor have fun taking ViaDesigner out for a spin - designing a sigma delta mixer.

Routing Interfaces Quickly & Efficiently on PCBs

In today's PCB designs, interfaces such as DDR pose major challenges for layout. Issues like timing and signal integrity can be tricky for even the most experienced designer. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about routing those tricky bits using a combination of automatic and manual routing techniques.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Timing Closure in FPGA Designs Made Easy with PlanAhead

In this episode of Chalk TalkHD Amelia chats with Frederic Rivoallon of Xilinx and they attempt to unravel the mysteries of timing closure and reveal that yes, you can get timing closure right the first time in your next design.

Smartphone and Tablet Accessory Design

In this episode of Chalk TalkHD Amelia Dalton talks to David Flowers from Microchip about creating tablet and smartphone accessories - and how it just may be easier than you think...

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

latest papers and content

Simulation Key to Automotive Challenges

This paper describes a new virtual prototyping environment that allows system integration to begin before physical hardware can be made available, a valuable commodity in today’s complex automotive system design process.  This new technology gives designers powerful tools for managing mechanics, electronics, software, and controls in one system with the capability to integrate the significant intersections between them.

Simulating Vector Controlled Induction Motors Using Space Vector Modulation

This paper illustrates the development of a comprehensive vector-controlled induction motor drive system using a virtual prototyping environment for the development/simulation of all designs. Motion control system development poses many challenges for conventional simulation tools. Not only are these systems extremely complex, they traverse both technology (domain) boundaries, as well as analog/digital boundaries. Conventional simulation tools cannot adequately deal with these diverse modeling requirements.

Allegro FPGA System Planner

The Cadence Allegro FPGA System Planner addresses the challenges that engineers encounter when designing one or more large-pin count FPGAs on the PCB board. By replacing manual error-prone processes with automatic pin assignment synthesis, this unique placement-aware solution eliminates physical design iterations while speeding optimum pin assignment.

Aldec Active HDL Datasheet

Active-HDL is an integrated FPGA Design and Simulation solution, with design entry, a high-performance mixed-language simulator and an easy-to-use, multi-vendor FPGA flow manager. Active-HDL has interfaces to over 80 leading EDA tools, making it the most powerful environment. Check out the top features and product configurations to see if Active-HDL is right for you.

Formal VIP for 100% Accurate Designs

In this week's Whiteboard Wednesdays video, Tom Hackett discusses formal verification IP (VIP), how it supports formal analysis, and how design engineers can leverage formal VIP to ensure their designs are 100% correct. Learn more about Cadence IP at http://ip.cadence.com.

How to Verify SoCs Incorporating the M-PCIe Specification

In this week's Whiteboard Wednesdays video, Mukul Dawar provides an overview of the Mobile PCIe (M-PCIe™) specification. He explains how Cadence VIP for M-PCIe can help you verify your mobile SoC design. Learn more about Cadence IP at http://ip.cadence.com.

Reduce Project Schedules and Increase Quality using Model Driven Development for Design, Verification, and Test

This paper shows how Model Driven Development can address common challenges in the system design, verification & testing of complex systems. Project success requires that hardware, software, and test teams fluently integrate application software, controlling firmware, analog and digital hardware, and mechanical components, which often proves to be costly in terms of time, money, and engineering resources. This paper covers such solutions that reduce project schedule while improving product release quality.

Modernizing System Development

Allowing disconnected development and waiting until the latest program stages to perform systems integration and connect all the pieces is a high risk situation, yet one all too common in today’s product realization process. Bringing domain expertise together as appropriate throughout a project’s development process is imperative for project success.  This paper explores a more modern approach to system development built on a Model Driven Development (MDD) approach.

Successfully Designing FPGA-Based Systems

One key challenge in successfully designing FPGA-based systems is choosing the right FPGA for the design needs, and maximizing the use of FPGA resources. In this paper Cadence offers recommendations for power-supply connections, pin selections and assignments, and other tips and methodologies to help customers design high-quality FPGA-based systems.

Addressing the “Power-Aware” Challenges of Memory Interface Designs

One of the toughest challenges in designing memory interfaces is accurately measuring timing while also considering fluctuations in power and ground rails due to simultaneously switching signals. Signal integrity (SI) engineers are increasingly insisting on “power-aware” SI analysis, where the effects of signal and non-ideal power/ground are considered when analyzing high-speed memory interfaces. This paper assesses how modern tools can be used to address power-aware SI challenges with I/O modeling, interconnect modeling, simulation, and analysis.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis Tech Packet

How to Effectively Manage Timing of FPGA Design Flow

When combined with advances in FPGA technologies for interface design efforts, EMA TimingDesigner can simplify design issues and provide advanced accurate control of virtually any interface. From simple SRAM interface protocols to high-speed source synchronous interface protocols, TimingDesigner allows designers to identify potential timing problems early in the design process and thereby providing the greatest opportunity to get the timing right the first time. This white paper will show you how to effectively integrate TimingDesigner with Xilinx and Altera Development Systems.

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PDN Design and FPGA Transceiver Performance

PDN designs targeting transceiver (SERDES) FPGAs require clean voltage sources with strict voltage rail requirements. This document describes the advantages of modern switching voltage regulators in a power distribution network (PDN) design to achieve the best FPGA transceiver performance. This white paper provides guidance on voltage regulator selection for low-noise applications, and a test case that demonstrates the transceiver performance for different types of voltage regulators and voltage rail configurations.

4K Format Conversion Reference Design

4K resolution is the next major enhancement in video because of the benefits in picture clarity and realism. Many leading projector, broadcast, and camera manufacturers are shipping 4K enabled systems. Altera enables this next generation format conversion by reducing the system device count, which lowers the overall costs, reduces the cost of development, and simplifies board design. Previous systems required as many as nine off-the-shelf devices to perform 4K format conversion—four 1080p format conversion devices and five devices for serial digital interface (SDI) input and output.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

Video Surveillance

In this video, Xilinx senior product line manager Joe Mallett shows how a mix of software and dedicated hardware in the Spartan allows an HD signal to be processed in real time, utilizing both VGA and QVGA formats.

UltraScale Devices Integrated 100G Ethernet IP Demo

See a demonstration of the integrated 100G Ethernet MAC and CAUI-4 IP available on UltraScale™ devices. This IP offers savings of up to 80K LUTs and 90% power over a soft implementation and simplifies your design process and time to market by providing proven functionality.

SmartFusion2 SoC FPGA Demo: Code Shadowing from SPI Flash to SDR Memory User’s Guide

This demo design shows SmartFusion®2 SoC FPGA device capabilities for code shadowing from serial peripheral interface (SPI) flash memory to single data rate (SDR) synchronous dynamic random access memory (SDRAM) and executing the code from SDR SDRAM. Code shadowing is a booting method that is used to execute an image from external faster volatile memories (DRAM) and is the process of copying the code from nonvolatile memory to volatile memory for execution. In performance critical applications, execution speed can be improved by code shadowing where code is copied to higher throughput RAM for faster execution.

Leveraging MIPI D-PHY-based Peripherals in Embedded Designs

Embedded systems designers face an ongoing dilemma. On the one hand they need to drive down systems costs. On the other they cannot exploit manufacturing economies of scale because their systems are targeted at relatively narrow, low volume applications. While high volume consumer markets offer components capable of performing similar tasks at much lower cost, embedded designers are restricted from taking advantage of those components by their systems’ reliance on highly specialized, legacy interfaces optimized for the embedded environment.

Using Low Cost, Non-Volatile PLDs in System Applications

Power supply sequencing, voltage and current monitoring, bus bridging, voltage level translation, interface control, and temperature measurement are typical board functions found in system applications. By using a programmable-based approach instead of several discrete devices or Application Specific Standard Products (ASSPs), designers can accelerate their time-to-market, address system cost and space reduction, and ensure a high level of product differentiation.

First Virtex UltraScale FPGA Demonstration

Watch a demonstration of the first device in the industry's only 20nm high end family—the Virtex® UltraScale™ VU095 device—featuring GTY transceivers capable of 32.75G short reach and 28.21G backplane operation, ideal for implementing next generation 400G and 500G wired networking systems.

Parameterizable Content-Addressable Memory

This application note describes a parameterizable content-addressable memory (CAM), and is accompanied by a reference design that replaces the CAM core previously delivered through the CORE Generator™ software. The CAM reference design should be used for all new FPGA designs targeting Virtex®-6, Virtex-5, Virtex-4, Spartan®-6, Spartan-3, Spartan-3E, Spartan-3A, Spartan-3A DSP FPGAs, and newer architectures. All the features and interfaces included in the reference design are backward compatible with the LogiCORE™ IP CAM v6.1 core. In addition, because the reference design is provided in plain-text VHDL format, the implementation of the function is fully visible, allowing for easy debug and modification of the code.

Overcome the Challenges of Highly Constrained Designs

Many of today's high-performance board designs have complex timing constraints, and meeting all those constraints can be a significant design challenge. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about advanced design techniques with PADS that will help get you to design closure faster and with fewer headaches on complex, highly-constrained boards.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Backplane Applications with 28nm FPGAs

This white paper covers the challenges of backplane applications and how to use the features of Altera® Stratix® V GX and GS FPGAs to address the range of problems that are encountered in backplane applications such as 10GBASE-KR.

Navigating the FDA Approval Process for Your Software Based Medical Device

Understand how to get your product to market within product launch schedules. Review challenges companies face as they seek FDA approval and review guidance and resources to assist with successfully navigating the approval process. Learn about a number of important areas including premarket submissions, documentation, verification and validation (V&V), user experience and human factors design, and cybersecurity.  Presented by Steve Robertson with Mentor Graphics Embedded Software.  

Analog Devices—Cadence VIP to Handle Transactions on APB and AXI Interface

Rohit Pandharipande, Design Engineer at Analog Devices, details working with Cadence migrating from VMM to the UVM-compliant Cadence(r) Verification IP (VIP) to verify a Dynamic Memory Controller.

Considerations Surrounding Single Event Effects in FPGAs, ASICs, and Processors

Single event effects (SEEs) are of a growing concern in high-reliability system development, yet there is much disparity among users of ASICs and FPGAs with regard to understanding how susceptible their designs might be.

Microchip's Accessory Framework for Android(tm)

The Microchip's Accessory Framework for Android provides a mechanism to transfer data to and from an Android application through the USB of the microcontroller.

Troubleshooting and Fast Fault Isolation with VTOS

Troubleshooting and quickly isolating faults is of tremendous value for reducing the time to redesign or repair failing boards. This process can cost a company millions of dollars each year. Supporting OMAP, Sitara, QorIQ, PowerQUICC and PowerPC, this paper describes how using an interpreter that allows the execution of a full test suite for verifying a design or an individual test for fault isolation can dramatically improve quality and reliability with Kozio’s Verification and Test OS (VTOS™). It describes how memory errors can be isolated to ECC (Error Control Coding), single-bit, row, column, and correlated to a part’s reference designator.


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