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MathWorks Connects to Hardware

The Maker movement is exploding right now, and most of the cool projects require doing some math. In this episode of Chalk Talk, Amelia Dalton chats with Amnon Gai of The MathWorks about using the powerful capabilities of MATLAB and Simulink in anything from your next maker hobby project to full-blown industrial designs.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

FPGA Product Support and EOL as Past Performance Indicators

This white paper presents the factors that lead to product obsolescence decisions made by FPGA vendors and how you can use this knowledge to craft obsolescence risk mitigation plans. This paper also introduces the idea of exercising Past Performance Assessments of FPGA vendors as both a risk and cost factor in making FPGA selection in military system design.

Virtex UltraScale VU440 FPGA Demonstration

See the new Virtex® UltraScale™ VU440, the world’s largest FPGA, in action being used to prototype 10 ARM® Cortex®-A9 CPUs.

What is Electrically Aware Design?

For years, layout tools have focused on the pins and wires, the "froms" and "tos", the segments and nets - without considering that they were really creating a complex electrical circuit. Today, however, the electrical properties of our layout is critical, and issues like parasitic resistance and capacitance can have a dramatic effect on our final design. In this episode of Chalk Talk, Amelia Dalton chats with John Stabenow of Cadence about electrically-aware design with Cadence's Virtuoso.

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.

Protium Rapid Prototyping Platform

Building a robust prototype involves a lot more than just throwing a bunch of big FPGAs on a board or in a box. In fact, success of a prototype is a lot more about the system surrounding the boards - the tools, design flow, and IP that make the whole thing come up easily and work smoothly. In this episode of Chalk Talk, Amelia Dalton talks to Juergen Jaeger of Cadence about the new Protium Rapid Prototyping Platform from Cadence, and how it can simplify your prototyping process.

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with David Stratman of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

Architecture Matters: Three Architectural Insights for SoC FPGAs

New devices that combine the power and flexiblility of FPGAs and conventional processors on a single chip represent a breakthrough in capability. But, understanding the complex architecture of these sophisticated components requires us to look under the hood to see how the architecture fits our design requirements, and how to choose the right chip for our application. In this episode of Chalk Talk, Amelia Dalton talks with Todd Koelling of Altera about what to look for in the architecture of your SoC FPGA.

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

PSpice Modeling

Join EMA for an on-demand webinar to learn more about part modeling in Cadence® PSpice®, the industry’s #1 analog simulator. We will highlight features such as creating parts from a datasheet, using vendor supplied models, and modifying existing parts.

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

Accelerating System Bandwidth with FPGAs and Hybrid Memory Cube

Move over DDR, the Hybrid Memory Cube (HMC) is here! But, from a design perspective, care and feeding of the amazing HMC can be a lot more demanding than DDR. In this episode of Chalk Talk, Amelia Dalton and Manish Deo of Altera explain how powerful FPGAs can help you tame the HMC in your next design.

FRAM Technology: The Next Generation of Non-volatile Memory for Microcontrollers

FRAM is one of the coolest non-volatile memory technologies to date. And, FRAM combined with microcontrollers is a perfect match. In this episode of Chalk Talk, Amelia Dalton chats with Will Cooper of Texas Instruments about the practical implications of FRAM technology in MCUs.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Accelerating Open Source Security Using OpenCL & Altera FPGAs

Today's FPGAs offer interesting potential for accelerating performance- and power-critical operations such as security algorithms. In this episode of Chalk Talk, Amelia Dalton chats with Ryan Kenny of Altera about using FPGAs to accelerate open source security algorithms written in OpenCL.

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

Infineon's 8th Generation of RF Transistors Maximize Receiver Sensitivity and Range

If you're designing systems that use the latest WiFi standards, you know that a great RF transistor with high gain and low noise is key to good performance. In this episode of Chalk Talk, Amelia Dalton talks with Andrew Nelson of Infineon about the latest in high-performance RF transistors - Infineon's new 8th generation.

chalk talks

Architecture Matters: Three Architectural Insights for SoC FPGAs

New devices that combine the power and flexiblility of FPGAs and conventional processors on a single chip represent a breakthrough in capability. But, understanding the complex architecture of these sophisticated components requires us to look under the hood to see how the architecture fits our design requirements, and how to choose the right chip for our application. In this episode of Chalk Talk, Amelia Dalton talks with Todd Koelling of Altera about what to look for in the architecture of your SoC FPGA.

Advanced Smart Display Solutions

In today's mobile designs, displays are one of the most important components in differentiating your product. As a result, more people are designing high-resolution displays into mobile devices. But, adding a high-res display to your design can be a complex task. In this episode of Chalk Talk, Amelia chats with Pavel Klinger (GLOBALFOUNDRIES) about GLOBALFOUNDRIES' solutions for the new generation of high-resolution smartphone displays.

Accelerated Design Productivity with the Kintex-7 FPGA Display Kit

In this episode of Chalk TalkHD Amelia gets into the guts of display technology with Aaron Behman of Xilinx. From the newest standards to the details of 4K2K, we will tell you how FPGAs are uniquely capable of meeting the extreme performance and power challenges posed by current and emerging video standards.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

MathWorks Connects to Hardware

The Maker movement is exploding right now, and most of the cool projects require doing some math. In this episode of Chalk Talk, Amelia Dalton chats with Amnon Gai of The MathWorks about using the powerful capabilities of MATLAB and Simulink in anything from your next maker hobby project to full-blown industrial designs.

Introducing Digitally Enhanced Power Analog

Analog power has always been the standard. New digital power modules offer great flexibility, but that comes with a price. For many applications, we'd love to have the simplicity and efficiency of analog power with the features of digital power. In this episode of Chalk TalkHD Amelia Dalton chats with Steve Stella from Microchip Technology about mixing the best of digital and analog power.

Integrated Design Environment for FPGA

Do you find that FPGA design flows can get a bit confusing and difficult to manage? What we really need is an integrated design environment that will help us keep our design activities organized. In this episode of Chalk TalkHD Amelia chats with Satyam Jani from Aldec about integrated design environments (IDEs) for FPGA design, why FPGA designers need a vendor-independent IDE, and how an FPGA-centric IDE can help us get through our design flow quite a bit more easily.

Verification Methodologies (Made Easy)

Most FPGA designers don’t know much about formal methodologies for verification. It’s too bad, because today’s complicated FPGA designs can really take advantage of standardized methodologies like UVM. In this episode of Chalk TalkHD Amelia and Jerry Kaczynski (Aldec) are going to unscramble the anagrams and get you on your way to understanding and harnessing the power of universal verification methodologies - so you can start applying them to your next design.

latest papers and content

Integrated Interlaken operating at 150 Gb/s in UltraScale FPGAs

This Virtex® UltraScale™ FPGA demonstration shows the newly integrated Interlaken IP core running at 150Gb/s over 12 lanes. By integrating Interlaken, Xilinx is able to reduce power consumption, logic utilization, and design complexity for one of the most popular protocols in networking today.

Virtex UltraScale VU440 FPGA Demonstration

See the new Virtex® UltraScale™ VU440, the world’s largest FPGA, in action being used to prototype 10 ARM® Cortex®-A9 CPUs.

Lower BOM Cost, Use 32-bit Wide LPDDR4 in Consumer Applications

In this week's Whiteboard Wednesdays video, the second of a two-part series, Jeffrey Chung discusses 32-bit applications and how LPDDR4 can be used most effectively.

New LPDDR4 Standard Features

In this week's Whiteboard Wednesdays video, the first of a two-part series, Jeffrey Chung discusses new LPDDR4 standard features that reduce power consumption and increase performance. Low-voltage interface standard logic (LVSTL) and data byte inversion (DBI) are discussed in detail.

What’s New in Capture 16.6

OrCAD 16.6 is here. Watch this free webcast to learn what's new in the latest release of OrCAD Capture, including enhancements in productivity, usability, and features. Highlights: • Database Enhancements • CIS Explorer Improvements & Customization • Tcl Expansion • SI Integration • Improved Symbol Creation

PSpice Modeling

Join EMA for an on-demand webinar to learn more about part modeling in Cadence® PSpice®, the industry’s #1 analog simulator. We will highlight features such as creating parts from a datasheet, using vendor supplied models, and modifying existing parts.

MathWorks Connects to Hardware

The Maker movement is exploding right now, and most of the cool projects require doing some math. In this episode of Chalk Talk, Amelia Dalton chats with Amnon Gai of The MathWorks about using the powerful capabilities of MATLAB and Simulink in anything from your next maker hobby project to full-blown industrial designs.

TimingDesigner 9.3

Meeting system timing is a major challenge for today’s high-speed digital interfaces. Sr. Applications Engineer Jerry Long, will show how TimingDesigner provides an interactive timing analysis environment that delivers fast and accurate results for timing critical designs.

CircuitSpace 5.0: Discover Why Design Reuse Has Never Been Easier or More Flexible

This webinar is designed for Hardware Engineers and PCB Designers requiring an easy to use, flexible, and comprehensive design reuse methodology to coexist with their current OrCAD and Allegro PCB design tools. It is intended for new users as well as current users of EMA CircuitSpace software and focuses on front-to-back reuse methodologies and incorporates the new and enhanced features of version 5.0. Learn how the CircuitSpace 5.0 feature set can expedite your PCB layout process.

Soundwire Audio Interface

In this week's Whiteboard Wednesdays video, the first of a two-part series, Charles Qi highlights the new MIPI audio interface standard, Soundwire. Charles details how Soundwire supports new audio applications and can connect to multiple audio interface devices.

Achieve DDR3 Signoff With Power-Aware Timing Analysis

Cadence and EMA have collaborated to provide a unique power-aware DDR timing sign off flow for complete cycle-accurate system level simulation and analysis. You can now sign off on your entire DDR interface with total confidence.

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A Significant Technology Advancement in High-Speed Link Modeling and Simulation

This white paper describes how Altera's jitter/noise eye (JNEye) link analysis tool enhances HSIO link modeling and simulation. This paper includes simulation and experimental results that demonstrate how the JNEye tool can meet the requirements for accuracy and advanced simulation and modeling techniques.

Implementing a Secure Boot with a Microsemi IGLOO2 FPGA

IGLOO®2 devices have a range of differentiated security features, including a secure boot feature, which verifies that the boot code used to ‘bring-up’ an embedded system is authorized to run on the target processor. Without this check of the MCU, a malicious intruder can compromise the entire system. This paper outlines the dangers of poor system security and illustrates how implementing a secure boot can dramatically increase the security of embedded systems. It also shows how secure boot may be included for free, since IGLOO2 FPGAs are used to implement many common embedded functions other than security.

EasyPath-6 Technology: Fast, Simple, Risk-Free FPGA Cost Reduction

Virtex®-6 FPGAs are the industry's leading platform for designing complex systems in the fields of wired and wireless communication, storage, computing, instrumentation, automotive, industrial, and medical. Virtex-6 FPGAs not only deliver the most attractive set of features and functionality and the fastest time to market advantage, they are also paired with EasyPath™-6 technology, the fastest path to cost reduction.

MachXO PLDs in System Control Designs

Introduction Temperature measurement, current monitoring, power supply sequencing, fan control and fault logging are typical board control functions used in complex circuit designs. System designers are faced with continual pressure to meet their development schedules, and need to implement control functions with minimal effort and risk while maintaining maximum flexibility.

5 Reasons to Put Your Processor on an FPGA

Did you know that soft-core FPGA processors provide unique benefits that you can’t achieve with commercial off-the-shelf systems? Learn five reasons why you should put your processor on an FPGA. Watch this 9-minute video to get more details on: Design flexibility, with a customizable peripheral set, Protection against processor obsolescence, Multi-core support, Hardware acceleration, Familiar software tools.

Understanding Single Event Effects (SEEs) in FPGAs

With the increasing popularity of programmable logic, FPGAs are finding their way into many applications that were once the territory of ASICs and ASSPs. At the same time, process nodes are shrinking and logic density is increasing, meaning that more of the system can be implemented in a single device. As programmable logic finds its way into avionics, communications and medical applications, designers face demands for increased reliability and safety over many of the traditional markets for FPGAs.

Configurable 10/40G Ethernet Solution

In this week's Whiteboard Wednesdays video, Arthur Marris discusses configurable options for Cadence 10/40G Ethernet MAC, integrated PCS, and SerDes IP.

Balancing Performance, Power, and Cost with the Kintex-7 FPGAs

In the past, FPGA vendors commonly segmented their portfolios between "high-end" and "low-cost" devices. However, as developers have refined the way they leverage FPGA technologies, they have voiced the need for a "mid-range" solution, featuring high-end functionality and performance in a cost effective package. The Xilinx® Kintex™-7 family of FPGAs was developed for these applications, delivering the most balanced power and performance in the industry while providing high-end features, such as cutting-edge transceivers, integrated IP, and extensive DSP resources.

The Exploding Variety of New Interfaces for Mobile SoCs

In this week's Whiteboard Wednesdays, Tom Hackett focuses on the wide variety of new and updated mobile interfaces for mobile SoCs. These interfaces are broken down into three catagories—SoC fabric, memory, and chip-to-chip—and include ARM AMBA 4, ARM AMBA 5, OCP, DDR, LPDDR, LPDDR3, LPDDR4, Wide I/O, Wide I/O2, DRAM, eMMC, eMMC5, UFS, CSI-3, SoundWire, USB, PCIe, and SSIC.

Verifying Your Designs with Simulation IP

In this week's Whiteboard Wednesdays installment, Tom Hackett takes a closer look at simulation verification IP (VIP), and how these IP cores help verify designs with protocol checks, test sequences, and other capabilities.

Introducing Innovations at 28nm to Move Beyond Moore’s Law (REVISED)

In addition to processing techniques, FPGA innovations allow Altera to move beyond Moore’s Law to meet higher bandwidth requirements while meeting cost and power budgets. Altera’s Stratix V FPGAs provide breakthrough bandwidth via 28-Gbps power-efficient transceivers, and allow users to integrate more of their design on a single FPGA by using Embedded HardCopy Blocks while increasing flexibility through partial reconfiguration.

OrCAD Data Management & Collaboration

Learn how EMA and Cadence are enabling the next generation of engineering data management workflows. This presentation will take you through a complete methodology covering design data management, component library management with automated footprint and symbol creation, and team based schematic design. These OrCAD engineering data management design technologies are geared to provide designers with purpose built tools to effectively manage your PCB data right from within your OrCAD design environment.

Zynq-7000 All Programmable SoCs Deliver Unmatched Performance and Power

Xilinx Zynq®-7000 All Programmable SoC devices fuse a fast processor system (PS) based on two 1GHz ARM Cortex™-A9 MPCore processors with the industry’s fastest and most advanced 28nm programmable logic (PL) fabric, a large on-chip memory, multiple high-speed serial transceivers, numerous hardened peripheral IP cores including DDR and Flash memory controllers, and an on-chip analog-processing block that incorporates two 1Msamples/sec A/D converters. Zynq-7000 devices offer unmatched performance with low operating power.

Implementing Next-Generation Passive Optical Network Designs with FPGAs (REVISED)

FPGAs play a key role for early adopters of next-generation passive optical network (PON) systems due to their flexibility to allow development of future proof designs and implementation of unique features to differentiate against competitors versus standard products. Altera® Stratix® V FPGAs’ abundant resources, robust transceivers with native PON burst mode support, and fast external memory interfaces bring an unprecedented level of system integration. Altera further helps to lower system cost and power consumption via its seamless migration path from FPGAs to its HardCopy® series ASICs.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

Designing with Vivado IP Integrator

Learn how Vivado® IP Integrator can be used to rapidly connect a Zynq® processor to the programmable fabric. Using built in board aware design rule checks and designer automation, Vivado can greatly improve user productivity.

Considerations Surrounding Single Event Effects in FPGAs, ASICs, and Processors

Single event effects (SEEs) are of a growing concern in high-reliability system development, yet there is much disparity among users of ASICs and FPGAs with regard to understanding how susceptible their designs might be.


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