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Battery Management Solutions

Designing battery-powered systems can be challenging. In addition to power and form-factor considerations, today's batteries require sophisticated charging and monitoring for maximum safety, life, and performance. In this episode of Chalk Talk, Amelia Dalton chats with Richard DelRossi of Texas Instruments about battery management solutions that can dramatically simplify your next battery-powered design while adding important monitoring capabilities to your device.

Overcome the Challenges of Highly Constrained Designs

Many of today's high-performance board designs have complex timing constraints, and meeting all those constraints can be a significant design challenge. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about advanced design techniques with PADS that will help get you to design closure faster and with fewer headaches on complex, highly-constrained boards.

How to Effectively Manage Timing of FPGA Design Flow

When combined with advances in FPGA technologies for interface design efforts, EMA TimingDesigner can simplify design issues and provide advanced accurate control of virtually any interface. From simple SRAM interface protocols to high-speed source synchronous interface protocols, TimingDesigner allows designers to identify potential timing problems early in the design process and thereby providing the greatest opportunity to get the timing right the first time. This white paper will show you how to effectively integrate TimingDesigner with Xilinx and Altera Development Systems.

USB Controller Connectivity

In this week's Whiteboard Wednesday video, Jacek Duda continues his discussion about USB controllers. This time, the conversation focuses on High-Speed Interchip Connectivity (HSIC) and Super Speed Interchip Connectivity (SSIC), and how they improve connectivity between multiple USB applications. Learn more about Cadence IP at http://ip.cadence.com.

Solving Today's Interface Challenges with Ultra-Low Density FPGA Bridging Solutions

Today’s embedded system designers face an unprecedented challenge from an I/O perspective. As system complexity rises, they are increasingly asked to address a multitude of potential I/O options. These options can range from interfacing one industry bus to another, to connecting new and higher performance sensors with mature application processors. Moreover, this problem is pervasive across all markets from high volume consumer applications to the latest industrial, scientific and medical systems.

Routing Interfaces Quickly & Efficiently on PCBs

In today's PCB designs, interfaces such as DDR pose major challenges for layout. Issues like timing and signal integrity can be tricky for even the most experienced designer. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about routing those tricky bits using a combination of automatic and manual routing techniques.

New Approach to Manage Electrical Complexity

Today's competitive and challenging environment, thought-leaders are recommending a shift to systems engineering. Using a systems engineering approach could help OEMs maintain product quality, reduce costs, manage change, and achieve time to market. This paper talks about applying systems engineering principles using the Capital tool suite to address these issues.

Xilinx and Open-Silicon HMC Memory Solution

Watch a demonstration of the industry's first available 12.5 Gb/s Hybrid Memory Cube (HMC) interface using the Xilinx Virtex®-7 FPGA. See how this solution provides superior memory bandwidth for your application using HMC technology, Virtex-7 FPGA, and Open-Silicon IP.

The Great Divide: Why Next-Generation FPGA Designs will be Hierarchical and Team-Based

This paper first considers the evolution of FPGAs and FPGA design. Next, the concepts of top-down and divide-and-conquer design flows are introduced. Also discussed are considerations and capabilities required to support true hierarchical team-based design along with content management and design reuse considerations.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform

Increasing design complexities and the rapidly increasing number of scenarios impede the timing closure process. ECO techniques that have good single-pass fix rates can reduce the number of iterations through the extraction, implementation, and final signoff loop for fastest timing closure.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Multiplying the Value of 20nm with UltraScale Devices: Doing More for Less

Xilinx is multiplying the value of 20nm with the UltraScale™ architecture and associated family of FPGAs and 3D ICs. Whether viewed from almost every attribute at the chip level or viewed when integrating multiple chips into one or fewer chips at the system level, you will find compelling value metrics as you migrate to an UltraScale solution. UltraScale architecture and Vivado® Design Suite are co-optimized to enable a device utilization target of 90%, which can result in up to a 30% effective cost advantage for the next generation of smarter, high performance systems in: Packet processing: Multi-hundred gigabit throughput Waveform processing: Multi-teraMAC throughput Image and video processing: 8K4K image and video processing and transport High performance computing: Multi-teraflop throughput Learn More about potential chip and system level value multipliers.

Maximize Your Power and Efficiency with PADS Interactive Placement and Routing

For the engineer doing desktop PCB layout, efficiency is important. You don't want to waste precious time fighting with your PCB tool, and you don't want to end up with lousy results because you and your tool weren't getting along. Mentor Graphics PADS provides an efficient, high-productivity interactive placement and routing environment that lets you get great results quickly. In this episode of Chalk Talk, Amelia Dalton talks to Jim Martens of Mentor Graphics about interactive layout using PADS.

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.

Cadence Tempus Timing Signoff Solution

Achieving timing closure for signoff can be a daunting challenge in today's complex designs. Meeting timing under all conditions - with the certainty required for signoff - is a complex and demanding task. In this episode of Chalk Talk, Amelia Dalton talks to Ruben Molina of Cadence Design Systems about the special challenges of signoff timing closure, and Cadence's new Tempus timing analysis tool.

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

Verify Design Performance with PADS Best-in-Class Simulation and Analysis

It really isn't important to simulate your PCB design - as long as you don't care about re-spins, signal integrity, cost... OK, actually, there are many good reasons to simulate your board. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about simulating your board design using PADS. It may make you re-think your board design strategy.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

chalk talks

DO-254 Requirements Traceability with Spec-TRACER

In this episode of Chalk TalkHD Amelia chats with Louie de Luna about Aldec's new Spec-TRACER tool and how Spec-TRACER helps you navigate your way through your design flow - from beginning to end, from requirements to verification.

Advanced Smart Display Solutions

In today's mobile designs, displays are one of the most important components in differentiating your product. As a result, more people are designing high-resolution displays into mobile devices. But, adding a high-res display to your design can be a complex task. In this episode of Chalk Talk, Amelia chats with Pavel Klinger (GLOBALFOUNDRIES) about GLOBALFOUNDRIES' solutions for the new generation of high-resolution smartphone displays.

Industrial Temperature Measurement Solutions

Many industrial designs need data from sensors such as temperature probes. But, getting from the analog world of probe signals to the digital world where the magic happens can be a tedious and tricky process. In this episode of Chalk Talk, Amelia Dalton talks with Sean Long of Maxim Integrated about an easy way to connect up sensors such as temperature probes in your next industrial design.

The Power of Tcl in PlanAhead

In this episode of Chalk TalkHD Amelia chats with Tori Darien from Xilinx about using Tcl in Xilinx’s PlanAhead tool for FPGA design. Amelia throws her some examples, and Tori walks us through how to work them using PlanAhead’s Tcl interface.

Battery Management Solutions

Designing battery-powered systems can be challenging. In addition to power and form-factor considerations, today's batteries require sophisticated charging and monitoring for maximum safety, life, and performance. In this episode of Chalk Talk, Amelia Dalton chats with Richard DelRossi of Texas Instruments about battery management solutions that can dramatically simplify your next battery-powered design while adding important monitoring capabilities to your device.

Value of Power Modules

Today, the cool kids aren’t using discrete components for power anymore. Nope. They’re using power modules. In this episode of Chalk TalkHD Amelia chats with Rich Nowakowski and Kevin Beals (Texas Instruments) about power modules, and why they’re the best solution for a wide range of design projects.

Smartphone and Tablet Accessory Design

In this episode of Chalk TalkHD Amelia Dalton talks to David Flowers from Microchip about creating tablet and smartphone accessories - and how it just may be easier than you think...

Routing Interfaces Quickly & Efficiently on PCBs

In today's PCB designs, interfaces such as DDR pose major challenges for layout. Issues like timing and signal integrity can be tricky for even the most experienced designer. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about routing those tricky bits using a combination of automatic and manual routing techniques.

latest papers and content

How to Effectively Manage Timing of FPGA Design Flow

When combined with advances in FPGA technologies for interface design efforts, EMA TimingDesigner can simplify design issues and provide advanced accurate control of virtually any interface. From simple SRAM interface protocols to high-speed source synchronous interface protocols, TimingDesigner allows designers to identify potential timing problems early in the design process and thereby providing the greatest opportunity to get the timing right the first time. This white paper will show you how to effectively integrate TimingDesigner with Xilinx and Altera Development Systems.

Using TimingDesigner with the Altera FPGA Design Flow

As technology advances, so does the complexity of problems it exposes. Nowhere is this more evident than in high-speed interface design. Timing issues previously deemed insignificant are now impacting design schedules and can no longer be dealt with after the fact. TimingDesigner from EMA Design Automation is the solution for just that. This application note will discuss the integration between TimingDesigner and Altera Quartus II enabling the exchange of critical timing data to ensure system timing closure.

Linking Early Mechatronic System Analysis to Physical Testing

Comprehensive testing is critical for many systems; however, system design and test development are often at opposite ends of a project’s schedule. Benefits accrue in improved system quality and on-time delivery when design and test are pursued concurrently.  Recent advances in modeling, simulation, and test technology provide the ability to link system design to system test well in advance of prototype availability. This paper describes the technologies required to improve test quality and reduce development cycles.

Concept to X: Ten Steps to Effective Model Driven Development

Model Driven Development is proven to improve productivity in the design process. It makes it possible to use models all the way down the flow, automatically generating parts of the design and thus improving the design’s quality by bringing in repeatability and standards compliance. It enables actions such as eliminating physical prototypes from the process, by instead simulating digital and analog elements working together and with the control software operating the system.

VeriSilicon and Cadence Customer Success Story

With the help of Cadence Software, VeriSilicon shortened their FPGA-based ASIC prototype development time by 75% and completed optimal pin assignment in one week vs. at least one month previously.

ASIC Prototyping Simplified

To use current solutions for application-specific integrated circuit (ASIC) prototyping using field-programmable gate arrays (FPGAs), you either have to create custom boards or buy off-the-shelf FPGA boards. Off-the-shelf boards don’t satisfy the requirements for complex systems on chips (SOCs), and they’re expensive and lack scalability. Cadence Allegro FPGA System Planner fills the gap, offering a simplified approach to ASIC prototyping.

Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform

Increasing design complexities and the rapidly increasing number of scenarios impede the timing closure process. ECO techniques that have good single-pass fix rates can reduce the number of iterations through the extraction, implementation, and final signoff loop for fastest timing closure.

USB Controller Connectivity

In this week's Whiteboard Wednesday video, Jacek Duda continues his discussion about USB controllers. This time, the conversation focuses on High-Speed Interchip Connectivity (HSIC) and Super Speed Interchip Connectivity (SSIC), and how they improve connectivity between multiple USB applications. Learn more about Cadence IP at http://ip.cadence.com.

A Methodology to Manage Mechatronic Development in Medical Electronic Products

Model Driven Development (MDD) dramatically reduces the risks of complex mechatronic system development, increases productivity within an FDA-regulated process, and automates collaborative development among disparate teams. An MDD flow gives the system integrator an effective platform from which to communicate the overall system requirements and can also tie project management into development and automate mundane/time-consuming tasks, so designers can spend their time doing what they do best – designing.

New Approach to Manage Electrical Complexity

Today's competitive and challenging environment, thought-leaders are recommending a shift to systems engineering. Using a systems engineering approach could help OEMs maintain product quality, reduce costs, manage change, and achieve time to market. This paper talks about applying systems engineering principles using the Capital tool suite to address these issues.

Verification Made Easy with Memory Models

In this week's Whiteboard Wednesday video, Tom Hackett explains memory models and their role in verifying memory interfaces in today's SoCs. He'll explain the differences betweeen memory models and simulation VIP, and talk about how they can help make verification a little easier. Learn more about Cadence IP at http://ip.cadence.com.

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more on demand

True Wireless Broadband

Mark Quartermain of Xilinx explains how the next generation of 4G digital cellular standards, Long Term Evolution, represents a significant step forward for wireless operators...and more!

Agile Mixed Signal Addresses Analog Design Challenges

Xilinx's Agile Mixed Signal technology offers a better way to scale and customize common analog interfaces requirements.

Avnet Zynq-7000 All Programmable SoC / AD9361 Software-Defined Radio Systems Development Kit

This video provides an introduction to the Zynq®-7000 All Programmable SoCs / AD9361 SDR System Development Kit. The kit provides a development platform that can be used to evaluate, prototype and accelerate the development of cognitive radio and wireless small cell applications on the Zynq-7000 family of devices and the ADI AD9361 RF Agile Transceiver. The Zynq family provides an ideal hardware solution for SDR applications that demand high performance, re-configurability and low power.

Hardware/Software Co-Verification of ARM Processor-Based Designs

In this episode of Chalk TalkHD Amelia chats with Lauro Rizzatti of EvE about the latest in emulation technology and explains how you can use emulation to dramatically accelerate software development, which is becoming the most time-consuming part of SoC design.

Leveraging OCP for Cache Coherent Traffic Within an Embedded Multi-core Cluster

Scaling processing performance beyond the frequency and power envelope of single core systems has led to the emergence of multi-core clusters. Data access management within such processing systems becomes essential to ensure behavioral consistency. One solution to provide access consistency is the application of a memory coherence model such as MESI or MOESI within the L1 data cache hierarchy. For the MIPS Technologies MIPS32® 1004K™ Coherent Processing System (CPS), we applied Open Core Protocol (OCP) point-to-point connectivity to establish snoop-based coherence throughout the cluster. Following are principles of this communication model.

Gate-Level Simulation Methodology

It is critical that teams begin GLS as early in the design cycle as possible, that the simulator run in high-performance mode, and that a proven simulation methodology be in place. This white paper explores new simulator use models and methodologies that boost GLS productivity, including extraction via static timing analysis and linting. Using these approaches, designers can focus on verifying real gate-level issues rather than waste expensive simulation cycles on re-verifying working circuits.

Xilinx Agile Mixed Signal

In this episode of Chalk TalkHD Amelia chats with Steve Logan (Xilinx ) and they're going to tell you all about Agile Mixed Signal, and how it can dramatically improve the capabilities of your next FPGA design.

Solutions for Mixed-Signal SoC Verification Using Real Number Models

As old methods fall short, new techniques make advanced SoC verification possible. This paper presents mixed-signal block and IC-level verification methodologies using analog behavioral modeling and combined analog and digital solvers. It then describes analog real number modeling (RNM) and how it is used in top-level SoC verification.

Streaming Multichannel Uncompressed Video in the Broadcast Environment

Designing video equipment for streaming multiple uncompressed video signals is a new challenge, especially with the demand for high-definition video streams. This white paper examines how a multichannel streaming PCIe DMA controller and other “building block” IP cores are combined within a Cyclone IV GX FPGA to support SD- and HD-SDI applications using an open-source video packet streaming-format protocol such as those used in non-linear editors, video servers, and video-capture applications.

AXI4 Interconnect Paves the Way to Plug-and-Play IP

In the past decade, the size and complexity of many FPGA designs exceeds the time and resources available to most design teams, making the use and reuse of Intellectual Property (IP) imperative. However, integrating numerous IP blocks acquired from both internal and external sources can be a daunting challenge that often extends, rather than shortens, design time. As today's designs integrate increasing amounts of functionality, it is vital that designers have access to proven, up-to-date IP from reliable sources.

Implementing Next-Generation Passive Optical Network Designs with FPGAs (REVISED)

FPGAs play a key role for early adopters of next-generation passive optical network (PON) systems due to their flexibility to allow development of future proof designs and implementation of unique features to differentiate against competitors versus standard products. Altera® Stratix® V FPGAs’ abundant resources, robust transceivers with native PON burst mode support, and fast external memory interfaces bring an unprecedented level of system integration. Altera further helps to lower system cost and power consumption via its seamless migration path from FPGAs to its HardCopy® series ASICs.

Streamline Your Video Processing Apps with Design Examples

Wouldn’t it be great if you could develop your video processing applications faster? You can with a complete suite of ready-to-use video processing functions. These functions are ready to be dropped into your design and connected through open Avalon® Streaming interfaces. Watch this 5-minute video for a demo that shows you a low-cost touch screen-based development kit running two design examples based on these functions.

UltraFast Vivado Design Methodology For Timing Closure

The methodology outlined in this training will enable you to achieve “Sign-Off” quality XDC constraints for timing closure. This methodology will also enable you to achieve timing closure significantly faster irrespective of the complexity of the design.

SmartFusion2 SoC FPGA – Dynamic Configuration of AHB Bus Matrix

SmartFusion®2 system-on-chip (SoC) field programmable gate array (FPGA) devices support advanced high performance bus (AHB) bus as a multi-layer AHB matrix. SmartFusion2 SoC FPGA devices AHB bus matrix has ten masters and seven direct slaves. This application note describes how to configure the weight values dynamically for the AHB bus matrix masters to access the AHB bus matrix slave using the weighted round-robin (WRR) arbitration. This application note also provides a reference design with two fabric masters connected to the FIC_0 and FIC_1 interfaces. The two fabric masters can access a single slave eSRAM1 using the WRR arbitration.

The Importance of IP at STMicroelectronics

Peter Hirt, IP Procurement & IP Partnership Manager at STMicroelectronics, details the role of IP in advanced node designs, IP provider requirements and Cadence's comprehensive IP portfolio.

Advantages of Using FPGAs in Precision Inverter Modules

This is a joint paper by ARADEX and Altera, which examines the advantages of using FPGA technology in high-precision servo drives compared to standard solutions based on microcontrollers or digital signal processors (DSPs). This paper also describes Altera's FPGA capability to execute many processes in parallel for complex systems without increasing the cycle time.

Xilinx and Huawei Discuss 400GE Networking

In this live presentation at OFC 2014, Huawei and Xilinx discuss how they are working together to solve the challenges associated with 400GE network readiness. This presentation also discusses the key technologies in 400GE and how programmable technology is playing a key role to expedite the development and deployment of Huawei's future IP router products in the networking infrastructure.

SDNet Overview with VP Nick Possley

Xilinx Vice President Nick Possley discusses how the new Software Defined Specification Environment for Networking (SDNet) is enabling 'Softly' Defined Networks, what benefits it's bringing to system architects and why it's considered revolutionary.


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