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Verify Design Performance with PADS Best-in-Class Simulation and Analysis

It really isn't important to simulate your PCB design - as long as you don't care about re-spins, signal integrity, cost... OK, actually, there are many good reasons to simulate your board. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about simulating your board design using PADS. It may make you re-think your board design strategy.

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

Static Timing Analysis and Constraint Validation

Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.

Intelligent PDF Generation

Often times it is necessary to share design information with other project members or partners who may not have access to a schematic capture tool or who you don’t want to have access to your design database. Creating a PDF is a perfect solution for this matter. Learn about how this new free OrCAD app enables you to create intelligent searchable PDFs.

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with David Stratman of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

Addressing Next-Generation Memory Requirements Using Altera FPGAs and HMC Technology

The white paper describes Altera(r) technology leadership in the serial memory interoperability space and describes the underlying hardware platform and controller architecture used to carry out a successful interoperability between Stratix(r) V FPGA and the HMC device. The document also includes real system-level examples where HMC solution provides an alternative solution to conventional memory-based solutions.

Protium Rapid Prototyping Platform

Building a robust prototype involves a lot more than just throwing a bunch of big FPGAs on a board or in a box. In fact, success of a prototype is a lot more about the system surrounding the boards - the tools, design flow, and IP that make the whole thing come up easily and work smoothly. In this episode of Chalk Talk, Amelia Dalton talks to Juergen Jaeger of Cadence about the new Protium Rapid Prototyping Platform from Cadence, and how it can simplify your prototyping process.

New Approaches to Hardware Acceleration Using Ultra Low Density FPGAs

Ask system designers to list the problems they face – it doesn’t matter whether they’re building mobile consumer, automotive, industrial, medical or scientific applications – and inevitably they’ll mention optimizing host processor performance. It’s hardly surprising. The event-driven architecture of these MPUs allows them to multitask and address new priorities as they occur. But as the number of I/O continues to rise, it also places escalating demand on bandwidth. Tasked with managing a wider array of I/O as well as other system-wide command and control functions, today’s host MPUs must remain operational for longer periods of time, thereby consuming precious power and compute resources.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

Accelerating System Bandwidth with FPGAs and Hybrid Memory Cube

Move over DDR, the Hybrid Memory Cube (HMC) is here! But, from a design perspective, care and feeding of the amazing HMC can be a lot more demanding than DDR. In this episode of Chalk Talk, Amelia Dalton and Manish Deo of Altera explain how powerful FPGAs can help you tame the HMC in your next design.

Maximize Your Power and Efficiency with PADS Interactive Placement and Routing

For the engineer doing desktop PCB layout, efficiency is important. You don't want to waste precious time fighting with your PCB tool, and you don't want to end up with lousy results because you and your tool weren't getting along. Mentor Graphics PADS provides an efficient, high-productivity interactive placement and routing environment that lets you get great results quickly. In this episode of Chalk Talk, Amelia Dalton talks to Jim Martens of Mentor Graphics about interactive layout using PADS.

Infineon's 8th Generation of RF Transistors Maximize Receiver Sensitivity and Range

If you're designing systems that use the latest WiFi standards, you know that a great RF transistor with high gain and low noise is key to good performance. In this episode of Chalk Talk, Amelia Dalton talks with Andrew Nelson of Infineon about the latest in high-performance RF transistors - Infineon's new 8th generation.

chalk talks

Timing Closure in FPGA Designs Made Easy with PlanAhead

In this episode of Chalk TalkHD Amelia chats with Frederic Rivoallon of Xilinx and they attempt to unravel the mysteries of timing closure and reveal that yes, you can get timing closure right the first time in your next design.

It's the Software, Silly! - Success with FPGA-based Prototyping

Software is becoming a larger and larger part of our system-on-chip (SoC) designs. It is critical that we be able to begin developing and debugging software as early as possible in the design cycle. But, the hardware part of today's complex designs takes months to stabilize. In this episode of Chalk Talk, Amelia Dalton talks with Juergen Jaeger of Cadence about the tight relationship between software and emulation and how you can achieve success in your SoC design with a comprehensive emulation strategy.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

Cadence Tempus Timing Signoff Solution

Achieving timing closure for signoff can be a daunting challenge in today's complex designs. Meeting timing under all conditions - with the certainty required for signoff - is a complex and demanding task. In this episode of Chalk Talk, Amelia Dalton talks to Ruben Molina of Cadence Design Systems about the special challenges of signoff timing closure, and Cadence's new Tempus timing analysis tool.

Integrated Design Environment for FPGA

Do you find that FPGA design flows can get a bit confusing and difficult to manage? What we really need is an integrated design environment that will help us keep our design activities organized. In this episode of Chalk TalkHD Amelia chats with Satyam Jani from Aldec about integrated design environments (IDEs) for FPGA design, why FPGA designers need a vendor-independent IDE, and how an FPGA-centric IDE can help us get through our design flow quite a bit more easily.

latest papers and content

UltraFast Embedded Design Methodology Guide

Xilinx is building on the success of its UltraFast™ Design Methodology with the new UltraFast Embedded Design Methodology Guide. The new Guide enables embedded design teams to improve productivity with a documented methodology for the creation of smarter systems leveraging Zynq®-7000 All Programmable SoCs.

PCIe Controller Solution

In this week's Whiteboard Wednesdays video, Sandeep Brahmadathan breaks down Cadence's high-performance, low-latency controller solution for PCI Express (PCIe).

Function Enablement with 8-bit PIC Microcontrollers

For a lot of mainstream applications these days, 32-bit or even 16-bit processors are serious overkill. You can get great performance, smaller footprints, lower power consumption, and lower cost using 8-bit devices. In this episode of Chalk Talk, Amelia Dalton talks with Wayne Freeman of Microchip Technology about function enablement with 8-bit MCUs.

Productivity Enhancements in OrCAD PCB Editor

This short video provides a compilation of recent productivity improvements added to OrCAD PCB Editor such as 3D Viewing, Multi Trace Routing, Arc Editing, and more.

Intelligent PDF Generation

Often times it is necessary to share design information with other project members or partners who may not have access to a schematic capture tool or who you don’t want to have access to your design database. Creating a PDF is a perfect solution for this matter. Learn about how this new free OrCAD app enables you to create intelligent searchable PDFs.

PrimeTime Special Interest Group (SIG) at SNUG Taiwan 2014

The Synopsys PrimeTime SIG is an active community for all PrimeTime users and design engineers who want to stay connected with the latest developments in the field of Static Timing Analysis (STA). PrimeTime SIG at SNUG Taiwan 2014 A PrimeTime SIG event, Accelerating Timing Closure with Advanced Technologies, was held in Hsinchu, Taiwan, during SNUG Taiwan on September 2, 2014. Customer speakers from ALi, MediaTek, and TSMC presented their timing analysis and closure experiences with PrimeTime advanced timing technologies. PrimeTime users and managers from top semiconductor companies attended the event.

Configurable 10/40G Ethernet Solution

In this week's Whiteboard Wednesdays video, Arthur Marris discusses configurable options for Cadence 10/40G Ethernet MAC, integrated PCS, and SerDes IP.

Flexible Design Reuse and Replication for PCB Editor

As PCB Designs become more complex and project timelines more compressed, it is important to identify opportunities to enhance design processes. See a quick introduction to CircuitSpace and learn how this productivity tool can help you reduces PCB layout time by up to 50%.

Automated Impedance and Coupling Checks

Cadence Sigrity Technologies provide the signal integrity and power analysis solutions needed for system-level verification and interface compliance so you can sign off in confidence. In this video you will learn how Sigrity makes it easy to quickly run Impedance and coupling checks on your design to identify areas of concern. In this example OrCAD PCB Editor was used as his tool of choice but the options are not limited to that. No models needed!

How to Automatically Replace LEF Abstracts with GDS IP

Physical Verification or other downstream analysis flow of P&R design data which only includes routing layers can miss issues caused by the current device level IP which is only represented by LEF abstracts. However, replacing the LEF IP abstracts with the current GDS version provided by layout teams can easily be merged with the DEF routing information and output to disk or in memory during Calibre Physical verification. This video steps through an example showing how to run this Calibre utility to merge the GDS data with DEF.

How to Waive DRC Results Using Calibre RVE

This video will show you how to waive some violations using Calibre RVE and re-use the waivers' information in the new set of results.

DDR Training Modes

In this week's Whiteboard Wednesdays video, Jeffrey Chung discusses the various training modes within the DDR interface. Watch to learn more about how these training modes can optimize timing.

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Virtex-6 FPGA Routing Optimization Design Techniques

With the ever-increasing need for high bandwidth, system designers continue to increase resource utilization when designing with Virtex®-6 devices. This can sometimes lead to routing challenges and congestion that can impact design closure. This white paper provides recommendations to help customers mitigate routing challenges in their Virtex-6 FPGA designs.

The Power Management IC for the Intel® AtomTM Processor E6xx Series and Intel® Platform Controller Hub EG20T

Time to market, cost, board size constraints, reliability and design capabilities are among the motivating factors in choosing Power Management IC versus a discrete solution. However, a discrete solution allows design optimization, offers higher power efficiency, flexibility and is easy to debug. Often, it is not possible to determine which choice will be better without understanding the details of design requirement. This paper aims to discuss both the advantages and disadvantages of using Power Management IC versus a discrete solution on the Intel® AtomTM Processor E6xx series platform.

Lowering Power at 28nm with Xilinx 7 Series FPGAs

This white paper describes several aspects of power related to the Xilinx® 28nm 7 series FPGAs, including the TSMC 28nm high-k metal gate (HKMG), high performance, low power (28nm HPLor 28 HPL) process choice. The power benefits afforded by the 28 HPL process and its usefulness across Xilinx's full product offerings is described as well as the architectural innovations and features for power reduction across the dimensions of static power, dynamic power, and I/O power.

LatticeECP3 Family

The LatticeECP3™ (EConomy Plus Third generation) family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES and high speed source synchronous interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture and the use of 65nm technology making the devices suitable for high-volume, high-speed, low-cost applications.

A Functional Test Approach for Counterfeit, Substandard, and High Risk Microcircuit Detection

The production and distribution of counterfeit parts is rising and finding their way into consumer and military devices. As counterfeiters get more sophisticated, so must the tests used for detecting counterfeit parts. A functional test strategy can provide an additional detection methodology that will exercise the device under a variety of operating conditions exposing functional deficiencies. This paper will discuss how establishing a functional baseline will define the bar for functional performance and can be very effective in detecting and stopping counterfeit parts from being shipping in assembled electronic devices. It describes how Verification and Test OS (VTOS™) provides an extensive functional test library that can be easily extended or modified to create an operational baseline to be used to detect counterfeit parts. VTOS can be used in engineering, as well as manufacturing, providing test consistency while in search for counterfeit parts. If functional testing is missing from your test strategy, now may be the time to reconsider its benefits.

MachXO2 Overview

Watch the 5-minute MachXO2 Overview Video to: See an overview of the MachXO2 product family, learn how MachXO2 lowers cost, lowers power and integrates system functionality, all in a small package, see how easy it is to start designing with MachXO2 devices with free design tools, IP trials and reference designs.

Designing with Multiple Industrial Ethernet Standards on a Single Hardware Platform

When developing and maintaining industrial communications hardware, supporting new or additional industrial Ethernet protocols often requires new hardware and corresponding software stacks. Rather than re-spinning your boards and migrating software code, you can save time and resources by choosing FPGAs.

Enabling High-Speed Radio Designs With Xilinx All Programmable FPGAs and SoCs

This white paper describes the capabilities of Xilinx® 7 series All Programmable FPGAs and SoCs to implement high-clock-rate signal processing functionality typically used by the datapath of digital radio applications.

The UltraFast Design Methodology for the Vivado Design Suite

The UltraFast™ Design Methodology is a comprehensive design methodology enabling accelerated and predictable design cycles, delivered through the Vivado® Design Suite, a methodology guide, design checklist, self-training video, instructor-led courses, and third party tools & IP cores.

Comparing 3D Memory Solutions and Their Market Applications

In this week's Whiteboard Wednesdays video, Scott Jacobson completes his three-part series on the Memory Wall with a discussion on the different 3D memory solutions available today and their market applications. You may recall that in the first segment, Scott examined how CPU performance outstrips memory transfers, and discussed options available to system designers, such as 2D solutions. In the second part of this series, Scott took a closer look at 2D memory solutions like EMMC 5.0, UFS, and DDR4.

Backplane Applications with 28nm FPGAs

This white paper covers the challenges of backplane applications and how to use the features of Altera® Stratix® V GX and GS FPGAs to address the range of problems that are encountered in backplane applications such as 10GBASE-KR.

The Great Divide: Why Next-Generation FPGA Designs will be Hierarchical and Team-Based

This paper first considers the evolution of FPGAs and FPGA design. Next, the concepts of top-down and divide-and-conquer design flows are introduced. Also discussed are considerations and capabilities required to support true hierarchical team-based design along with content management and design reuse considerations.

Video Sneak Peek: Industry’s First 28-Gbps FPGA

If you are seeking a device that is fast, reliable, and gives you high bandwidth, seek no further. Our 28-nm Stratix® V FPGAs are just what you need for your high-end designs such as 100G applications. Watch this 5-minute video to get an initial look at our high-performance Stratix V FPGA running at 28 Gbps. You will: See the transmit eye at 28 Gbps running a PRBS-31 test pattern, See the receiver performance at 28 Gbps, and learn about the transceiver architecture that provides high performance, power efficiency, and reliability.

Powering Stratix V FPGAs (Made Easy)

Getting the right power to your FPGA has gotten a lot more complicated, but it doesn’t have to mess up your day or cut into your golf time. In this episode of Chalk TalkHD Amelia chats with Jordon Inkeles (Altera) and Sharad Khanal (Linear Technology) about pairing Altera’s Stratix V FPGAs with Linear Technology’s power modules for a clean, robust, reliable power solution.

PowerPC to MIPS® Architecture Migration Guide (REVISED)

Software investment is the biggest ticket item in any project. Hence it is important to choose an instruction set architecture (ISA) that offers a truly scalable solution for future development. To address various embedded market segments, MIPS Technologies offers distinct, binary-compatible families of processor cores that span applications from 32-bit microcontrollers all the way to 64-bit multi-threaded, superscalar many-core processors for networking infrastructure, and numerous digital consumer markets in between. Since one can seamlessly scale the performance range between a wide array of processors, the MIPS® architecture offers an ideal path for protecting software investment on a new design or a follow-on/upgrade to an existing project. This paper illustrates the ease of migration from the Power to MIPS architecture, and highlights the areas that users need to focus on during this process.

Improving Hardware Verification with Accelerated Verification IP (VIP)

In this week's Whiteboard Wednesdays video, Tom Hackett talks about Accelerated Verification IP (VIP) and how it makes hardware verification more efficient and productive.

Hardware/Software Co-Verification of ARM Processor-Based Designs

In this episode of Chalk TalkHD Amelia chats with Lauro Rizzatti of EvE about the latest in emulation technology and explains how you can use emulation to dramatically accelerate software development, which is becoming the most time-consuming part of SoC design.


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