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System Design with Advance FPGA Timing Models

Advanced FPGAs are difficult to characterized due to their advanced process nodes, which delays the availability of final timing models until silicon characterization is completed. This paper describes the timing models available for end-user FPGA design, in advance of production FPGAs. This paper explains the development cycle of FPGAs, along with the timing models available at each stage. This paper also describes the best practices that you can use at each stage of the timing model.

Xilinx and Open-Silicon HMC Memory Solution

Watch a demonstration of the industry's first available 12.5 Gb/s Hybrid Memory Cube (HMC) interface using the Xilinx Virtex®-7 FPGA. See how this solution provides superior memory bandwidth for your application using HMC technology, Virtex-7 FPGA, and Open-Silicon IP.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Battery Management Solutions

Designing battery-powered systems can be challenging. In addition to power and form-factor considerations, today's batteries require sophisticated charging and monitoring for maximum safety, life, and performance. In this episode of Chalk Talk, Amelia Dalton chats with Richard DelRossi of Texas Instruments about battery management solutions that can dramatically simplify your next battery-powered design while adding important monitoring capabilities to your device.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

15Gb/s HMC Interface for UltraScale Devices

Watch a demonstration of the industry's first 15Gb/s HMC interface by Xilinx and Pico Computing at the International Supercomputing Conference.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

Announcing ProtoCompiler for Multi-FPGA Prototyping

Prototyping Automation and Debug Software for HAPS FPGA-Based Prototyping Systems Improves Prototyping Performance

Overcome the Challenges of Highly Constrained Designs

Many of today's high-performance board designs have complex timing constraints, and meeting all those constraints can be a significant design challenge. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about advanced design techniques with PADS that will help get you to design closure faster and with fewer headaches on complex, highly-constrained boards.

Verify Design Performance with PADS Best-in-Class Simulation and Analysis

It really isn't important to simulate your PCB design - as long as you don't care about re-spins, signal integrity, cost... OK, actually, there are many good reasons to simulate your board. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about simulating your board design using PADS. It may make you re-think your board design strategy.

What is Design Security in a Mainstream SoC?

Do you worry about security in your FPGA design? Are there bad guys out there trying to take advantage of security holes in your electronic designs? What can we do to stop them? In this episode of Chalk Talk, Amelia chats with Tim Morin (Microsemi) about the practical aspects of security in mainstream SoC FPGAs - what threats are out there and what we can all do to help keep the bad guys at bay.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Industrial Temperature Measurement Solutions

Many industrial designs need data from sensors such as temperature probes. But, getting from the analog world of probe signals to the digital world where the magic happens can be a tedious and tricky process. In this episode of Chalk Talk, Amelia Dalton talks with Sean Long of Maxim Integrated about an easy way to connect up sensors such as temperature probes in your next industrial design.

Cadence Tempus Timing Signoff Solution

Achieving timing closure for signoff can be a daunting challenge in today's complex designs. Meeting timing under all conditions - with the certainty required for signoff - is a complex and demanding task. In this episode of Chalk Talk, Amelia Dalton talks to Ruben Molina of Cadence Design Systems about the special challenges of signoff timing closure, and Cadence's new Tempus timing analysis tool.

Accelerating System Bandwidth with FPGAs and Hybrid Memory Cube

Move over DDR, the Hybrid Memory Cube (HMC) is here! But, from a design perspective, care and feeding of the amazing HMC can be a lot more demanding than DDR. In this episode of Chalk Talk, Amelia Dalton and Manish Deo of Altera explain how powerful FPGAs can help you tame the HMC in your next design.

Static Timing Analysis and Constraint Validation

Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.

Solving the ASIC Prototype Partition Problem with Synopsys ProtoCompiler

When developing a multi-FPGA prototype of an ASIC or SOC, you have many decisions to make: how to distribute clocks; where to put the daughter boards with real-world interfaces; which modules should be assigned to each FPGA; where and how many cables connect the FPGAs; and how to squeeze all the signals into those cables. All these decisions need to result in the fastest possible prototype that you can build and debug in the allotted time. And every week the RTL changes, and sometimes it seems that every decision you make forces you to revisit all the decisions that came before.There is a better way.

100G Ethernet Packet Parsing with Spacetime

Designing 100G Ethernet is a daunting challenge. Timing, power, latency, and throughput all fight with each other, and it's easy to fall into a design trap with a solution that doesn't offer a good compromise. In this episode of Chalk Talk, Amelia Dalton chats with Parsun Raha about the challenges of 100G (and beyond), and how those conflicting design goals can be met by Tabula's innovative Spacetime architecture.

Leveraging MIPI D-PHY-based Peripherals in Embedded Designs

Embedded systems designers face an ongoing dilemma. On the one hand they need to drive down systems costs. On the other they cannot exploit manufacturing economies of scale because their systems are targeted at relatively narrow, low volume applications. While high volume consumer markets offer components capable of performing similar tasks at much lower cost, embedded designers are restricted from taking advantage of those components by their systems’ reliance on highly specialized, legacy interfaces optimized for the embedded environment. This issue plays out most vividly in displays, cameras and application processors where low-cost, MIPI-compliant components for mobile platforms with interfaces based on the D-PHY physical bus cannot communicate with embedded system processors that typically feature LVDS, RGB or SPI interfaces for their display and digital parallel, subLVDS or HiSPi interfaces for an image sensor. This paper looks at potential solutions to this problem and explores how embedded systems designers can leverage the cost/performance advantages system developers in high volume consumer markets have already learned.

Advanced Smart Display Solutions

In today's mobile designs, displays are one of the most important components in differentiating your product. As a result, more people are designing high-resolution displays into mobile devices. But, adding a high-res display to your design can be a complex task. In this episode of Chalk Talk, Amelia chats with Pavel Klinger (GLOBALFOUNDRIES) about GLOBALFOUNDRIES' solutions for the new generation of high-resolution smartphone displays.

chalk talks

GLOBALFOUNDRIES RFCMOS Solutions and Catena WiFi Solutions

In this episode of Chalk TalkHD Amelia Dalton chats with Fayyaz Singaporewala (GLOBALFOUNDRIES) and Mats Carlsson (Catena) about how to get that scary RF portion of your next design done in a snap.

Accelerating System Bandwidth with FPGAs and Hybrid Memory Cube

Move over DDR, the Hybrid Memory Cube (HMC) is here! But, from a design perspective, care and feeding of the amazing HMC can be a lot more demanding than DDR. In this episode of Chalk Talk, Amelia Dalton and Manish Deo of Altera explain how powerful FPGAs can help you tame the HMC in your next design.

How to Design a Sigma Delta Mixer Circuit

In parts 1 & 2 of this 3-part Chalk Talk series, we talked about how Triad Semiconductor can save you 75%, or even as much as 99% in your next mixed-signal ASIC design. But, what good is savings if you don't know what you can design with it? In this third episode of our 3-part Chalk Talk series, Amelia and Reid Wender of Triad Semiconductor have fun taking ViaDesigner out for a spin - designing a sigma delta mixer.

Powering Stratix V FPGAs (Made Easy)

Getting the right power to your FPGA has gotten a lot more complicated, but it doesn’t have to mess up your day or cut into your golf time. In this episode of Chalk TalkHD Amelia chats with Jordon Inkeles (Altera) and Sharad Khanal (Linear Technology) about pairing Altera’s Stratix V FPGAs with Linear Technology’s power modules for a clean, robust, reliable power solution.

Building a New Type of IP Factory

Reliable IP blocks are essential to the success of most modern SoC and custom IC designs. But finding a reliable, reputable source of verified IP can be challenging. In this episode of Chalk Talk, Amelia Dalton talks to Kevin Yee (Cadence Design Systems) about Cadence's substantial IP offerings

Vault-Driven Electronics Design

In this episode of Chalk TalkHD Amelia chats with Ben Jordan of Altium about how to set up a robust design-for-re-use design methodology for your team that will flow nicely with your project, won’t take much effort to set up, and will bring BIG TIME long-term benefits of design re-use, configuration management, and manufacturing handoff.

Maximize Design Productivity With PCIe/104 FPGA/Processor

In this episode of Chalk TalkHD Amelia chats with Christine Van De Graaf of Kontron, who explain how Kontron is incorporating pre-made, small form factor boards, a high-performance embedded processor programmable logic into their new MSMST board and how we can get started designing with one.

The Hardware Prototype Arrives -- Find Design Errors Fast and Improve Design Quality

In this episode of Chalk TalkHD Amelia chats with Bob Potock (Kozio) about how you can save yourself a bunch of headaches at prototype time and how Kozio’s VTOS (Verification and Test Operating System) can solve all of your embedded design prototyping problems.

latest papers and content

Injecting Automation into Verification - Assertions

What we will show in this webinar is how we can leverage Assertions, including the pre-defined, pre-tested OVL libraries, to automate the verification process further. What we will also show is the way in which the Assertion Manager will create pre-configured checkers as well as how to debug the results of an assertion failing. As the monitoring of the Assertions is done fully automatically by the simulator this further reduces the load of the engineer during verification and regression.

Strategies to Develop Secure and Robust Embedded Devices

Learn a pragmatic approach to configuring a heterogeneous multicore ARM® device built with ARM TrustZone™ technology and trade-offs of various implementations.

Verifying Solid State Drives Incorporating NVM Express

In this week's Whiteboard Wednesday video, Mukul Dawar explains the NVM Express protocol and considerations to keep in mind when using verification IP to perform functional verification.

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

15Gb/s HMC Interface for UltraScale Devices

Watch a demonstration of the industry's first 15Gb/s HMC interface by Xilinx and Pico Computing at the International Supercomputing Conference.

Xilinx and Open-Silicon HMC Memory Solution

Watch a demonstration of the industry's first available 12.5 Gb/s Hybrid Memory Cube (HMC) interface using the Xilinx Virtex®-7 FPGA. See how this solution provides superior memory bandwidth for your application using HMC technology, Virtex-7 FPGA, and Open-Silicon IP.

Leading Up to PCI Express 4.0

In this week's Whiteboard Wednesdays video, Moshik Rubin discusses the history of the PCI Express standard. Moshik starts with PCIe Gen1, which originated in 2002, and walks through the doubling of throughput offered by each new generation, ending with PCIe Gen4.

Selecting an Operating System (OS) for Embedded Application

It seems these days, just about every embedded system has some type of operating system. And there are more options today as to which OS to choose. Is open source your best choice? What about a free RTOS? In this paper, learn the pros and cons of the many OS options available today and how to select the right OS for your next embedded project.

Navigating the FDA Approval Process for Your Software Based Medical Device

Understand how to get your product to market within product launch schedules. Review challenges companies face as they seek FDA approval and review guidance and resources to assist with successfully navigating the approval process. Learn about a number of important areas including premarket submissions, documentation, verification and validation (V&V), user experience and human factors design, and cybersecurity.  Presented by Steve Robertson with Mentor Graphics Embedded Software.  

Using USB IP Controllers in Today's Devices

In this week's Whiteboard Wednesdays video, Jacek Duda follows up on his earlier video focused on USB performance and now takes a closer look at USB IP controllers and their roles in today's devices.

Protium Rapid Prototyping Platform

Building a robust prototype involves a lot more than just throwing a bunch of big FPGAs on a board or in a box. In fact, success of a prototype is a lot more about the system surrounding the boards - the tools, design flow, and IP that make the whole thing come up easily and work smoothly. In this episode of Chalk Talk, Amelia Dalton talks to Juergen Jaeger of Cadence about the new Protium Rapid Prototyping Platform from Cadence, and how it can simplify your prototyping process.

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DO-254 Requirements Traceability with Spec-TRACER

In this episode of Chalk TalkHD Amelia chats with Louie de Luna about Aldec's new Spec-TRACER tool and how Spec-TRACER helps you navigate your way through your design flow - from beginning to end, from requirements to verification.

Advantages of Using FPGAs in Precision Inverter Modules

This is a joint paper by ARADEX and Altera, which examines the advantages of using FPGA technology in high-precision servo drives compared to standard solutions based on microcontrollers or digital signal processors (DSPs). This paper also describes Altera's FPGA capability to execute many processes in parallel for complex systems without increasing the cycle time.

Maximize Design Productivity With PCIe/104 FPGA/Processor

In this episode of Chalk TalkHD Amelia chats with Christine Van De Graaf of Kontron, who explain how Kontron is incorporating pre-made, small form factor boards, a high-performance embedded processor programmable logic into their new MSMST board and how we can get started designing with one.

Optimize Power and Cost with Altera’s Diversified 28nm Device Portfolio (REVISED)

Altera’s 28-nm devices provide a diversified product portfolio tailored to support a broad spectrum of applications, ranging from low cost and power, to high-end applications. This white paper describes the power and cost advantages of Altera’s Stratix® V, Cyclone® V, Arria® V, and HardCopy® V devices.

Battle Board Demo: Virtex-7 FPGA GTH Transceiver vs. Altera Stratix V GX Transceiver

As designers clamor for 10G+ chip-to-chip and backplane performance, they rely on receiver equalization to compensate for signal distortion. Watch this side-by-side comparison of equalization capabilities of the Xilinx® Virtex®-7 FPGA GTH transceiver vs. the Altera Stratix V GX transceiver.

Maria Marced, President, TSMC Europe, on the Importance of 16nm FinFET Technology

Maria Marced, President of TSMC Europe, discusses with Christian Malter, Director Technology Solutions, EMEA, Cadence, the significance of 16nm FinFET technology and highlights their collaboration with Cadence.

System Design with Advance FPGA Timing Models

Advanced FPGAs are difficult to characterized due to their advanced process nodes, which delays the availability of final timing models until silicon characterization is completed. This paper describes the timing models available for end-user FPGA design, in advance of production FPGAs. This paper explains the development cycle of FPGAs, along with the timing models available at each stage. This paper also describes the best practices that you can use at each stage of the timing model.

Effective Version Control for Electronic Design

When it comes to our hardware engineering projects, we need to keep our design data well organized. In the software world, this is accomplished with the help of version control systems. Unfortunately, most of us don’t learn version control for hardware design. In this episode of Chalk TalkHD Amelia chats with Ben Jordan of Altium about how effective version control can help every step of the design process, enable team design, manage versions and configurations, and keep our project from spiraling out of control.

Learn How Dev Kit Utilities Shorten the Design Process

Are you looking for a way to speed up the design process for your low-power FPGA applications? This 10-minute video will give you a closer look at the Cyclone® III LS FPGA Development Kit, particularly two utilities that accelerate the design cycle – the Board Test System and the Board Update Portal. You'll see the Cyclone III LS FPGA Development Kit in action and find out how this device can support your cost-sensitive, bandwidth-intensive applications.

Taming the Challenges of 20nm Custom/Analog Design

Custom and analog designers will lay the foundation for 20nm IC design. However, they face many challenges that arise from manufacturing complexity. The solution lies not just in improving individual tools, but in a new design methodology that allows rapid layout prototyping, in-design signoff, and close collaboration between schematic and layout designers.

Implementing Always-On Audio

In this week’s Whiteboard Wednesdays episode, Gerard Andrews, from the Tensilica Audio DSP Group at Cadence, discusses always-on audio functionality. Gerard details features like voice trigger, sensor fusion, and low-power audio playback, and explains how Cadence’s HiFi DSP solution can help you successfully implement always-on audio technology in today’s mobile devices.

Building a Custom Verification GUI with System Console

Want to know how to easily create GUI dashboards to interact with your design? Watch this new demo to learn how to: Add run-time visibility into your FPGA systems, access available run-time information using Tcl, a flexible command language, create your own custom verification tool using graphical elements such as buttons, dials, and graphs and develop solutions ranging from simple scripts to sophisticated GUI applications

Leveraging Power Leadership at 28nm with Xilinx 7 Series FPGAs

In this new whitepaper, learn the most effective methods for minimizing FPGA power consumption with Xilinx's industry-leading power solutions. Real-world design examples showcasing Xilinx power estimation and optimization methods are discussed.

What's New in Vivado 2014.1

Learn what's new in the Vivado® Design Suite 2014.1. We'll review the new lightweight installer, introduce the Xilinx Tcl Store and wrap-up with the new Timing Constraints Wizard.

OpenCL on FPGAs: Accelerating Performance and Design Productivity

FPGAs have amazing capabilities when it comes to accelerating performance-critical algorithms at a tiny fraction of the power it would require to run them in software. The marriage of FPGAs with conventional CPUs could provide a truly remarkable high-performance computing platform. However, the problem has always been how to program it. In this episode of Chalk TalkHD Amelia chats with Albert Chang of Altera about about how OpenCL can now be used to program FPGAs. OpenCL is already very popular for programming systems with graphics processors (GPUs). Now, Altera has enabled us to use this same language to program FPGA+CPU systems.

MAX Series Configuration Controller Using Flash Memory

Altera’s flash memory configuration controller provides an alternative configuration solution for high-density FPGA-based designs. With the flexibility to use a bigger flash memory to store more configuration data, designers can implement the flash memory controller in MAX series devices for use in Stratix series, Arria series, and Cyclone series FPGAs. Configuration bitstream sizes are increasing with the higher-density FPGAs, which require larger devices to store and configure data.

Accelerating DSP Designs with the Total 28-nm DSP Portfolio

Implementing DSP datapaths with different performance, precision, IP, and development flows is challenging and labor intensive. As more and more high-performance DSP datapaths are implemented on FPGAs, Altera has developed a complete DSP solutions portfolio at 28 nm to address these challenges and speed up the design cycle for FPGA-based applications. This white paper discusses the different components of this portfolio and how they come together to accelerate the implementation of a DSP design.

Simulating MicroBlaze design using Synopsys VCS in Vivado

Learn how to run simulation with MicrBlaze™ IPI design using Synopsys VCS simulator in Vivado®. We will provide a demonstration on how to compile simulation libraries, generate simulation scripts for an IP or an entire project and then run simulation.


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