Optimizing 10-Gbps Backplane Performance on Stratix V FPGAs

With our Transceiver Signal Integrity Development Kit, Stratix V GX Edition and the Transceiver Toolkit tool in Quartus II software, you can easily and efficiently evaluate the performance of the high-speed serial transceivers in the Stratix V FPGA.

Watch this 7-minute video to:

See a 10GBASE-KR backplane demo using the Transceiver Signal Integrity Development Kit, Stratix V GX Edition
Learn how to use Transceiver Toolkit to observe and improve link performance
See the effects of signal conditioning on the receiver's margin using Altera's EyeQ tool

Want to Read More? Please Sign In

If you have already registered with us, you can sign in here to access this content. If not, register now and get full access to our entire On Demand library of webcasts, white papers and more. Registration is free. Click Here to Register

Comments:

You must be logged in to leave a reply. Login »

Full Whitepaper Available for Download

If you already have registered with us, Sign In Here

Not a member yet? Register now!

It's free and will give you access to this and our entire collection of webcasts, videos, whitepapers and more. Register Now

Sign In Register

On Demand from Altera

It's 2022: Do You Know What Your FPGA Is?

Reducing Power Consumption and Increasing Bandwidth on 28-nm FPGAs

Optimizing 10-Gbps Backplane Performance on Stratix V FPGAs

Meeting the Low Power Imperative at 28 nm (REVISED)

Achieving Lowest System Cost with Midrange 28 nm FPGAs

More On Demand From Altera

Recent Article Mentions

New Dimension in Chips

What 3D ICs Mean for the FPGA Industry

Coming Back for Seconds

Design West 2012 Part Two

(Moore’s) Law of Diminishing Return

When Do We Have Enough?

Spring into Action

Calypto’s Power Optimization and the Find Amelia at Design West Contest

Getting Your Verification Ducks in a Row

Recent Company News

Nallatech Packs Altera Stratix V FPGA, Dual SFP+ and DDR3 SDRAM into Low-Profile, PCIe Gen 3 Network Processing Card

Synopsys, Altera and TSMC Collaborate to Deliver Silicon-Accurate Parasitic Modeling and Extraction for 28-nm Processes

Molex Partners with Altera and Gennum to Demonstrate 100 Gbps Enabling Technology at OFC/NFOEC

LDRA Tool Suite Directly Integrates with Altera’s Nios® II Embedded Design Suite

Altium collaborates with Altera to release new online component resources and software support