MachXO2 Family

The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from 256 to 6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI controller, I2C controller and timer/counter. These fea-tures allow these devices to be used in low cost, high volume consumer and system applications.

The MachXO2 devices are designed on a 65nm non-volatile low power process. The device architecture has several features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low microwatt static power for all members of the family.

The MachXO2 devices are available in two versions – ultra low power (ZE) and high performance (HC and HE) devices. The ultra low power devices are offered in three speed grades -1, -2 and -3, with -3 being the fastest. Sim-ilarly, the high-performance devices are offered in three speed grades: -4, -5 and -6, with -6 being the fastest. HC devices have an internal linear voltage regulator which supports external VCC supply voltages of 3.3V or 2.5V. ZE and HE devices only accept 1.2V as the external VCC supply voltage. With the exception of power supply voltage all three types of devices (ZE, HC and HE) are functionally compatible and pin compatible with each other.

The MachXO2 PLDs are available in a broad range of advanced halogen-free packages ranging from the space saving 2.5x2.5 mm WLCSP to the 23x23 mm fpBGA. MachXO2 devices support density migration within the same package. Table 1-1 shows the LUT densities, package and I/O options, along with other key parameters.

The pre-engineered source synchronous logic implemented in the MachXO2 device family supports a broad range of interface standards, including LPDDR, DDR, DDR2 and 7:1 gearing for display I/Os.

The MachXO2 devices offer enhanced I/O features such as drive strength control, slew rate control, PCI compati-bility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and bus-keeper features are controllable on a “per-pin” basis.

A user-programmable internal oscillator is included in MachXO2 devices. The clock output from this oscillator may be divided by the timer/counter for use as clock input in functions such as LED control, key-board scanner and sim-ilar state machines.

The MachXO2 devices also provide flexible, reliable and secure configuration from on-chip Flash memory. These devices can also configure themselves from external SPI Flash or be configured by an external master through the JTAG test access port or through the I2C port. Additionally, MachXO2 devices support dual-boot capability (using external Flash memory) and remote field upgrade (TransFR) capability.

Want to Read More? Please Sign In

If you have already registered with us, you can sign in here to access this content. If not, register now and get full access to our entire On Demand library of webcasts, white papers and more. Registration is free. Click Here to Register


 
    submit to reddit  

Comments:

it is very good
Posted on December 24, 2010 at 3:42 AM
What's going on - I think pdf is corrupt
http://www.eejournal.com/files/....../DS1035.pdf...
Posted on February 18, 2013 at 3:15 AM
amelia You should now be able to download the datasheet. Thank you for bringing this to our attention.
Posted on February 18, 2013 at 1:29 PM
You must be logged in to leave a reply. Login »

Full Whitepaper Available for Download

If you already have registered with us, Sign In Here

Not a member yet? Register now!

It's free and will give you access to this and our entire collection of webcasts, videos, whitepapers and more. Register Now

Sign In  Register

Recent Article Mentions

FPGAs in the IoT

Lattice iCE40 Ultra Brings Programmability to Wearables

Smaller, Cheaper SerDes

Lattice ECP5 Proves Less is More

Google's Smartphone Revolution

Inside Project Ara

Proliferating Programmability in 2014

Forecasting the FPGA Future

Sensor Hub Partitioning

Not Just Software vs. Hardware


Login Required

In order to view this resource, you must log in to our site. Please sign in now.

If you don't already have an acount with us, registering is free and quick. Register now.

Sign In    Register