A Synthesis & Partitioning Strategy for Effective Multi-FPGA Prototyping

by Nang-Ping Chen, Auspy, Inc. and Ehab Mohsen, Mentor Graphics

Prototyping an ASIC, ASSP, or SoC onto a single FPGA is not without its challenges. You have to deal with differences in ASIC and FPGA architectures, optimize for performance and area requirements, and account for a debug strategy. Unfortunately, this is only the tip of the iceberg when tasked with implementing an ASIC onto a multi-FPGA platform. Currently, the largest FPGAs have a capacity of roughly 1.5 M equivalent ASIC gates, so when prototyping a chip larger than this, a multi-FPGA strategy must be in place, and several more pitfalls must be accounted for.

And yet it is well worth the effort. Over the years, FPGA prototyping has proven indispensable for functional verification and early software integration. With mask costs approaching $3M for 45nm designs, avoiding a re-spin by prototyping with FPGAs is a small price to pay—even if it means a minor deviation from the final ASIC environment (e.g., clocking, memories, and speed). The larger the design, the more development and manufacturing cost. These larger designs must be partitioned into several FPGAs if they are to be prototyped. It comes as no surprise that for multi-FPGA prototyping, a little pre-planning can go a long way.

 

FPGAs and the IC Bubble

The Techonomics of Programmability

by Kevin Morris

Exponentials are exciting!

Anything in the real world that follows an exponential curve is a recipe for increased adrenalin production. If we're bopping along in our normal linear lives, and we bump into a geometric progression, we (those of us that took math, anyway) naturally expect that we're in for a short and exciting ride. Something that happens in twos or fours today will be exploding into the 128s and 256s by the end of the week, and next month will be flaming out in the bazillions. Although these events can have huge amplitudes, their short duration typically prevents the integral from amounting to much, and their lasting effect is minimal.

What the heck was that last paragraph talking about?

Let's come back from the arena of abstract arithmetic for a bit and drop into the real world. Your e-mail box catches a less-than-funny forward from one of those "forwarding friends," (the type that sends you about twelve uninteresting e-things each day - ranging from virus alerts to chain letters to pictures of political candidates with farm animals photoshopped to their heads.) If you're early in the wave, you may see the e-joke only once this week. Next week, however, you'll get three copies - the week after, maybe sixty - and the week after that they'll fill your spam bucket as the exponential explosion of forwards gets the joke to every man, woman, and child in the world with more bandwidth than reading time. By the fourth week, the joke is gone completely, flamed out in a fiery flash of fuel deprivation. The world - largely unchanged from the event.

 

Braving the Black-and-White

ISSCC Highlights

by Bryon Moyer

You can’t figure out whether it’s a bad dream or just a dream. You’re gliding down an escalator towards a large, subterranean space. All you see is black and white, as if color has been banished from the building. Despite your misgivings, the escalator delivers you into the monochromatic morass. Shoulder-to-shoulder suits explain the chromatic deficit. Interactions are formal, even stilted. Snippets of banter range from the banal to the arcane. You question whether you could cast a cogent contribution into any of the conversations, whether you really belong here. You pinch yourself; you try to shake yourself awake. And you realize… it’s not a bad dream. It’s not a dream at all. It’s ISSCC, one of the least commercial of conferences for chip makers. You’re in a foyer full of engineers on a coffee break between sessions. Not a logo or company banner in sight. Marketing dudes not welcome. It’s about substance, not style. Go technical or go home.

 

Simplifying DDR

Mentor’s New DDR Wizard

by Bryon Moyer

Over in one of our sister pubs, we did a review of some of the challenges of DDR last year. In particular, DDR3 has some incredible timing subtleties that have to be managed. DDR controllers are available as IP for FPGAs, but they still have to be connected to the memories on the board. And those board connections can seriously affect whether or not the timing requirements of the DDR protocols are properly met.

Mentor has just announced new versions of their HyperLynx PI and SI board power integrity products, and the SI one has a briefly-mentioned little feature that I got to see in action at DesignCon; apparently they’re finding that this “oh and by the way” thing is much more than a trivial add-on. It’s a wizard that allows you to specify how you’ve configured your DDR controller and then check out whether the timing passes muster. It can handle DDR, DDR2, and DDR3. A lot of the popularity seems to be with FPGA applications (although it can be used with other controllers as well). Granted, this is a board design tool, but this is where board meets FPGA.

 

Free Linux Microprocessor*

(Some Restrictions Apply)

by Jim Turley

In keeping with our theme of free stuff (see Embedded Technology Journal, January 27, 2009) we proudly chronicle the newest free alternative for embedded developers: a free Linux-compatible microprocessor. Never has so much been offered to so many for so little. Or something like that.

Here’s the deal. Altera, the world’s second-best-known FPGA company, has struck a deal with Wind River Systems, the world’s second-best-known embedded-software company, to port Linux to Altera’s NIOS II processor. And since NIOS is free, you’ve got yourself a free 32-bit microprocessor capable of running a genuine full-on multitasking Linux operating system.

 

Free Linux Microprocessor*

(Some Restrictions Apply)

by Jim Turley

In keeping with our theme of free stuff (see Embedded Technology Journal, January 27, 2009) we proudly chronicle the newest free alternative for embedded developers: a free Linux-compatible microprocessor. Never has so much been offered to so many for so little. Or something like that.

Here’s the deal. Altera, the world’s second-best-known FPGA company, has struck a deal with Wind River Systems, the world’s second-best-known embedded-software company, to port Linux to Altera’s NIOS II processor. And since NIOS is free, you’ve got yourself a free 32-bit microprocessor capable of running a genuine full-on multitasking Linux operating system. Naturally, there’s a catch. In fact, there are two. First off, NIOS is free only if you’re already using Altera’s FPGA chips (more on this later). Second, the Linux itself isn’t free; Wind River charges a significant amount of money for access to the software, and even more money for annual support.

That’s right – the microprocessor is free but the open-source software costs money. One wonders how such a paradox came to be.


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