A Passel of Processors

NVIDIA’s Tesla T10P Blurs Some Lines

by Kevin Morris

Picture this architecture – a high speed application processor doing control coupled to an accelerator comprised of a mass of processing elements ready to power-parallelize compute-intensive components of a complex problem. Sound familiar? Supercomputers have taken advantage of acceleration using schemes like this for a while. People using FPGAs for co-processors do it all the time.

Now, picture a new chip with 1.4 billion transistors, an array of 240 cores, and a processing throughput equivalent to about 1 TeraFLOPS. Many readers of this publication would probably guess a new FPGA, right?

 

Broken Design Flows and Point Tools

by Dick Selwood

Where do you go for help when your design flow is broken? Wally Rhines of Mentor Graphics wants it to be to him and his company. He feels that the EDA tool chain breaks every 2.5 process nodes (and has some convincing PowerPoint slides to back his case), and that 45 nanometre is the next inflexion point.

Stemming from this he argued, when giving a Globalpress Electronics Summit Keynote, it takes a broken tool chain to get engineers to adopt new tools. And who can blame them? Apart from the cost of purchase, it is hard work changing to a new design tool. You have to learn not just how to use the tool but also how to use it to take advantage of short cuts, building on the tool’s strengths and working round the weaknesses, all the things you already know how to do with your existing tools. But you also have to build libraries, sort out the interfacing problems with other tools, and devise a sensible path for legacy code. Even if the tool works out of the box there is still a load of other things you need to do. It is logical to go on using the existing tool for as long as you can -- and engineers are nothing if not logical.

The argument is that the move from schematic to code, from RTL to high level languages and now from high level languages to ESL tools -- all these took place only because the users had no choice but to make the change to a new tool set if they were to continue to get working chips into production.

 

Shortening the Rope

LDRA Checks Cert C and MISRA C++

by Bryon Moyer

Once upon a time, a man was given a rope and was told that it would be useful for many things. That most anything could be done with that rope. And the man tried it out, found some things easy to do – tying a bow, for example – and some things hard – intricate cat’s cradle, for example. He found that he could tie large crab traps together on such a rope and run them out to sea and retrieve them later. But he also learned that having his foot in a coil as the pots were put out could be deadly. He found that heavy items could be hoisted by tying a loop at the end and running the rope over a branch, or, better yet, a pulley. He also found that putting his head through that loop was not a good idea. He decided to name this rope, and he called it “C.”

Then he received a new kind of rope -- not three-dimensional, but six-dimensional. This rope could do anything the old rope could do and much more. It was more difficult to comprehend, and the implications of what could be done were not always obvious. And observed behaviors in the three or four standard dimensions might hide unexpected and unobserved behaviors in the fifth or sixth dimension. But it gave him great power to do great things, far beyond what was practical with C, even if he didn’t always know exactly what he was doing. And he named this “C++.”

 

Performance Improvements with New Secure IP and FAST Simulation Mode Models

by Howard Walker, Xilinx, Inc.

Today’s high-capacity and high-performance FPGA designs are becoming more complex and require more third-party intellectual property (IP) cores. These hard IP blocks include pecialized high-speed multi-gigabit transceiver (MGT) I/O cores, PCI Express cores, clock management modules, FIFOs and complex processor cores, such as the PPC440 in the Virtex5 device. The DSP clock management cores (DCMs), BlockRAMs, and FIFO models are in a class of Hard IP cores provided in standard libraries because the simulation models do not require source code protection. However, the other class of Hard IP cores, which includes MGT I/O cores, PCI Express, TEMAC, and PPC440 cores, requires that the simulation source files be protected. Until now this last set of hard IP models was provided to customers as SmartModels, which have support limitations, and ease-of-use and performance issues. Recent developments in the HDL language standards and support for these new standards by simulation tool providers now allow Xilinx to provide hard IP models for the Virtex-5 Family of Platform FPGAs using SecureIP libraries instead of SmartModels. SecureIP models provide FPGA designers with significant ease of use and performance advantages over SmartModels.

 

Employing an I/O Interlocutor

FMCs Decouple FPGAs from Complex I/Os

by Bryon Moyer

It used to be so simple. PLDs provided a medium by which you could create and modify logic without having to make any board changes. All the variability was on the inside; the outside consisted of I/Os, and, back in the day, that meant one thing: TTL. Eventually, when CMOS became more prevalent, the less-often-used rail-to-rail CMOS interface was available, but those I/Os were on different devices that were dedicated to the CMOS low-power market.

Well, the first hints that the age of innocence was coming to an end appeared with the lowering of the power supply voltage from 5 V to 3.3 V. This was mostly managed through more careful I/O design so that, if possible, a 3.3-V I/O could tolerate 5-V signals when it was connecting to a device that was still on a 5-V supply. Yeah… remember when we scratched our heads wondering how one would manage two – count them, TWO! – supplies on a board? No longer could we ignore the I/O and simply focus changes on the internals of the PLD. The I/O now became part of the design work.

 

Shortening the Rope

LDRA Checks Cert C and MISRA C++

by Bryon Moyer

Once upon a time, a man was given a rope and was told that it would be useful for many things. That most anything could be done with that rope. And the man tried it out, found some things easy to do – tying a bow, for example – and some things hard – intricate cat’s cradle, for example. He found that he could tie large crab traps together on such a rope and run them out to sea and retrieve them later. But he also learned that having his foot in a coil as the pots were put out could be deadly. He found that heavy items could be hoisted by tying a loop at the end and running the rope over a branch, or, better yet, a pulley. He also found that putting his head through that loop was not a good idea. He decided to name this rope, and he called it “C.”


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