A Twist on Simulate Versus Synthesize
It’s crunch time. The prototype for our board has been spun and is in transit back to our lab for testing. The project is already two weeks behind schedule thanks to late changes to the spec and problems discovered during signal integrity analysis of the layout. It’s been good for me because, quite frankly, I needed those two weeks to get my test bench to where I am satisfied that I have done due diligence to the simulation.
The project has been coded in VHDL, and I have taken a fairly disciplined approach – maintaining hierarchy throughout, using entity declarations for all black-boxes, primitives and macros (so the design is more portable and meets the IEEE standard as much as possible), and a mostly RTL-styled approach. Of course, some of my design is behavioral, or else I have ignored the major benefit of HDLs altogether – the ability to use behavioral abstraction.
Is That My FPGA Burning?
We've talked about power a lot on these pages over the past year. We've told about advances in power optimization and estimation, struggles with leakage current at smaller geometries, clock gating, configuration peaks, and a bunch of other hot topics in cool FPGA design. All of these late-breaking developments are wonderful if you already know the starting point. However, many of our readers have pointed out that we could use a little more background. It's not that exciting to find out that leakage current has been reduced by 50% if you don't know what the leakage current was to begin with, whether it was a problem, and what direction it was going before.
So, for those people, we present our FPGA Power Primer. This article should give you a nice base map for your exploration of the power landscape in FPGAs. If you've done lots of electronic design outside the FPGA world, pay particular attention. Power in FPGAs probably doesn't work the way you think. The rules, assumptions, and results are different (and often counter-intuitive) compared with, say, power consumption in processors.
NVIDIA’s Tesla T10P Blurs Some Lines
Picture this architecture – a high speed application processor doing control coupled to an accelerator comprised of a mass of processing elements ready to power-parallelize compute-intensive components of a complex problem. Sound familiar? Supercomputers have taken advantage of acceleration using schemes like this for a while. People using FPGAs for co-processors do it all the time.
Now, picture a new chip with 1.4 billion transistors, an array of 240 cores, and a processing throughput equivalent to about 1 TeraFLOPS. Many readers of this publication would probably guess a new FPGA, right?
You never know with CEOs these days. There was a time when there was a certain order to things, a level of formality. CEOs would set themselves apart, and, in emulation of that, so would their teams. Mahogany Row represented the corporate pantheon, and veneration was the expected order of the day. Fallibility would be, if not brushed off outright as beyond possibility, at least not broached. We’ve probably all known some old-school CEOs. The ones you can’t speak to unless spoken to first. The ones that like to keep their execs guessing what it is they want. The ones that are all stick, no carrot. The ones that change the rules frequently and arbitrarily so that no one gets too comfy.
But these days, well, you just never know. Heading into a conversation with Magma’s Rajeev Madhavan, I wasn’t sure what to expect. I had met him only briefly as he prepared for his MUSIC keynote speech a couple months ago. At that time, like anyone, he was preparing to go on stage, and so, while congenial, his mind and style were focused on the upcoming presentation. Not necessarily representative of what his day-to-day style might be.
Developing Safety Critical Software and Systems
This article has been in production for some time. It was going to be so simple: chat to two of the leading pundits on system safety and pull together a quick piece of “compare and contrast.” Just to add to the timeliness, there has been a very genteel firefight over the role of the IEC 61508 standard on the leading system safety newsgroup (http://www.cs.york.ac.uk/hise/sc_list.php), and, sadly, Air France flight 447 has disappeared, leading to intense speculation as to whether the cause was related to the fly-by-wire systems that the Airbus 330’s (and other Airbus models) use extensively.
Saving Engineering Education
When most of us went to engineering school, we planned to immerse ourselves in the ocean of technology. Our education started with foundations of mathematics and science, and then, like some giant tech-history-TiVo, fast-forwarded us through centuries of experience and innovation to get us to a point somewhere near the state-of-the-art at the time of our graduation.
We soon learned that our engineering degree was simply a license to learn, however. In an environment of exponential change (as evidenced by Moore's Law), the actual technology we mastered in our educational process was probably obsolete before our first day of professional engineering work. It's not that our education wasn't valuable. It's just that the part we needed had nothing to do with the using the TEGAS simulator, throwing down transistors on a CALMA station, or our mad FORTRAN coding skills.