Performance Improvements with New Secure IP and FAST Simulation Mode Models

by Howard Walker, Xilinx, Inc.

Today’s high-capacity and high-performance FPGA designs are becoming more complex and require more third-party intellectual property (IP) cores. These hard IP blocks include pecialized high-speed multi-gigabit transceiver (MGT) I/O cores, PCI Express cores, clock management modules, FIFOs and complex processor cores, such as the PPC440 in the Virtex5 device. The DSP clock management cores (DCMs), BlockRAMs, and FIFO models are in a class of Hard IP cores provided in standard libraries because the simulation models do not require source code protection. However, the other class of Hard IP cores, which includes MGT I/O cores, PCI Express, TEMAC, and PPC440 cores, requires that the simulation source files be protected. Until now this last set of hard IP models was provided to customers as SmartModels, which have support limitations, and ease-of-use and performance issues. Recent developments in the HDL language standards and support for these new standards by simulation tool providers now allow Xilinx to provide hard IP models for the Virtex-5 Family of Platform FPGAs using SecureIP libraries instead of SmartModels. SecureIP models provide FPGA designers with significant ease of use and performance advantages over SmartModels.

 

Employing an I/O Interlocutor

FMCs Decouple FPGAs from Complex I/Os

by Bryon Moyer

It used to be so simple. PLDs provided a medium by which you could create and modify logic without having to make any board changes. All the variability was on the inside; the outside consisted of I/Os, and, back in the day, that meant one thing: TTL. Eventually, when CMOS became more prevalent, the less-often-used rail-to-rail CMOS interface was available, but those I/Os were on different devices that were dedicated to the CMOS low-power market.

Well, the first hints that the age of innocence was coming to an end appeared with the lowering of the power supply voltage from 5 V to 3.3 V. This was mostly managed through more careful I/O design so that, if possible, a 3.3-V I/O could tolerate 5-V signals when it was connecting to a device that was still on a 5-V supply. Yeah… remember when we scratched our heads wondering how one would manage two – count them, TWO! – supplies on a board? No longer could we ignore the I/O and simply focus changes on the internals of the PLD. The I/O now became part of the design work.

 

Shortening the Rope

LDRA Checks Cert C and MISRA C++

by Bryon Moyer

Once upon a time, a man was given a rope and was told that it would be useful for many things. That most anything could be done with that rope. And the man tried it out, found some things easy to do – tying a bow, for example – and some things hard – intricate cat’s cradle, for example. He found that he could tie large crab traps together on such a rope and run them out to sea and retrieve them later. But he also learned that having his foot in a coil as the pots were put out could be deadly. He found that heavy items could be hoisted by tying a loop at the end and running the rope over a branch, or, better yet, a pulley. He also found that putting his head through that loop was not a good idea. He decided to name this rope, and he called it “C.”

 

Sticking to Plan

Javelin and Magma Move Floorplanning Towards Production

by Bryon Moyer

Floorplanning has become an important step in SoC design because it lets designers and managers get an early sense of what can be accomplished on a given piece of silicon. This is, of course, critical during the never-ending negotiation between design and marketing as to who’s on drugs and who’s sandbagging. It’s more or less the equivalent of doing furniture planning, where you draw a picture of a room and cut out rough scale versions of the furniture and move them around to get a rough sense of what will fit. Not particularly accurate, certainly not good enough for production, but much better than those back-of-the-envelope calculations that get more and more ambitious with every beer.

As such, however, floorplanning has been something of a dead-end operation. The design gets partitioned and assigned, and that part of the work most likely follows the design through to completion. But then the approximations and calculations start, with rough synthesis and placement and a high level of reliance on familiar blocks that have already been done before, so you kind of know what they’ll require. This work contributes to the planning and commitments of feature set, die size, and performance, but then it is largely abandoned as the “real” design gets going in earnest. Floorplanning is freely touted as a prototyping tool, not as a development tool.

 

New Toys

by Dick Selwood

When you are exposed to around 40 companies presenting their latest and greatest products or philosophy, it is sometimes a little difficult to keep the b……t filter in full-on mode. On your behalf, I tried to be as cynical as possible at the Globalpress World Summit in San Francisco, trying to see through each professional presentation and slick use of PowerPoint to establish whether there was a grain of truth in its heart. (Of course all of us at Techfocus are experts in finding that grain of truth – but normally we get more than a few minutes between presentations to restore our sense of perspective.)

There were enough grains of truth amongst the chaff to make it worth giving you two reports: this one will look at some of the new gizmos or technologies that seem to be fun or whose impact on the world is still a little way out, while the next one will look at some of the more serious stories and those that will have a more immediate impact.

 

New Kid in Class

SiliconBlue Debuts Low-Power FPGAs

by Kevin Morris

There’s a new kid in class.

We’ve all been through this scenario before. All the players are comfortable in their established roles. The leader tries to stay ahead and always communicates with the purpose of maintaining the perception of leadership. The second player vies constantly with the leader for supremacy and mind-share, always trying to one-up the alpha dog. The third through fifth players are constantly flanking, trying to differentiate and establish themselves based on supremacy in a particular niche.

For years now, Xilinx, Altera, Lattice, Actel, and QuickLogic have tried, taunted, and tested each other in the programmable logic market. One could almost model it with Bruce Tuckman’s 1965 Forming – Storming - Norming – Performing model for describing the stages of group development. For the past few years, the FPGA class has been Performing. Now, a new kid just walks in and sits down. Everybody has to re-think and re-group. SiliconBlue is here.


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