Posted on January 13, 2012 at 5:52 PM

There are conference ramp-ups and then there is the CES ramp-up...in this week's Fish Fry, I check out some of the not so fabulous gritty bits from the CES marketing machine...and I give away a MAX V CPLD Development Kit courtesy of Altera and you can win if you tell me what architecture is Max V based on?

Posted on January 13, 2012 at 6:38 PM

So altera'a humkkhnkhn... "Speak loudly"

So ALTERA'S MAX V CPLD is based on LUT Architecture called Look Up Table based LAB (Logic Array Block).

Are you coming to RTECC-MEDS Confs at Santa Clara, CA.

Thank you
Parag Dave

Posted on January 13, 2012 at 7:16 PM

The *real* secret of Alera's MAX V CPLD is that it's based on a low-cost, low-power, non-volatile architecture!

How long have CPLDs been storing configuration information in FLASH and running from an SRAM copy? I've been out of the loop for too long...

Posted on January 13, 2012 at 7:35 PM

The secret sauce in the Altera MAX V CPLD is the non-volatile architechture.

Posted on January 13, 2012 at 9:09 PM

The secret is that the Max V CPLD thinks its an FPGA, with high-speed global interconnects, PLLs, onchip memory and oscillator blocks.

These features are commonly found on more costly FPGA devices, but the space saving architecture employed in the MAX V family has allowed Altera to include these features in a CPLD family.

Max V CPLDs also offer up to 50% lower total power than other CPLD solutions and can often run off a single voltage supply.

Posted on January 14, 2012 at 9:58 AM

Price. Programmable logic isn't just for prototyping and small series. It can be used for final mass-production products.

Compare it with MCU. There is no 300MHz MCU for that money. Speed.

Example: boot your design fast from flash/ROM with CPLD, but who gonna boot CPLD? Yeah, flash on chip. Even there is some for me.

But real secret of MAX CPLD and why it should be best friend of every hardware engineer is performance predictability and simplified design. All that MultiTrack interconnect, LABs, LUTs, local interconnect, carry chains are made for simple routing and fast compilation, just to make easier life for us designers. Those who ever work with FPGAs knows horror of "It failed timing constrain". Software cannot be smarter when hardware is dumb.

Posted on January 18, 2012 at 7:37 AM

MAX V devices contain a two-dimensional row- and column-based architecture to
implement custom logic. Row and column interconnects provide signal interconnects
between the logic array blocks (LABs)

Posted on January 18, 2012 at 9:52 AM

It has a non-volatile architecture and a two-dimensional row, column-based architecture connecting Logic Array Blocks (LABs).

Posted on January 18, 2012 at 2:54 PM

The Altera MAX V architecture is loaded with "Awesome (tm)". By building the CPLD with "Awesome (tm)", Altera has been able to produce a device with unparalleled coolness. Even their FPGAs are envious. Well, only the older FPGAs, because the Cyclone V, Arria V, Stratix V devices are also filled with "Awesome (tm)".

Oh, wait...this post isn't sponsored...


The Altera site says:

The groundbreaking MAX V CPLD architecture (Figure 1) includes an array of logic elements (LEs grouped in logic array blocks (LABs)), memory resources (non-volatile flash and LE RAM), digital PLLs, global signals (clocks or control signals), and a generous amount of user I/Os. The MultiTrack interconnect is designed to maximize performance and minimize power by using the most efficient, direct connection from input to logic to output. Find more details about the MAX V architecture in the MAX V Device Family Data Sheet (PDF).


Kevin M.